105 lines
3.4 KiB
Diff
105 lines
3.4 KiB
Diff
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From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar>
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Date: Wed, 4 Nov 2015 13:13:42 -0300
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Subject: [PATCH] mtd: pxa3xx_nand: Fix initial controller configuration
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The Data Flash Control Register (NDCR) contains two types
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of parameters: those that are needed for device identification,
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and those that can only be set after device identification.
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Therefore, the driver can't set them all at once and instead
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needs to configure the first group before nand_scan_ident()
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and the second group later.
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Let's split pxa3xx_nand_config in two halves, and set the
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parameters that depend on the device geometry once this is known.
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Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -1419,34 +1419,43 @@ static int pxa3xx_nand_waitfunc(struct m
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return NAND_STATUS_READY;
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}
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-static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
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+static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
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{
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struct platform_device *pdev = info->pdev;
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struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
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- struct pxa3xx_nand_host *host = info->host[info->cs];
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- struct mtd_info *mtd = host->mtd;
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- struct nand_chip *chip = mtd->priv;
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- /* configure default flash values */
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+ /* Configure default flash values */
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+ info->chunk_size = PAGE_CHUNK_SIZE;
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info->reg_ndcr = 0x0; /* enable all interrupts */
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info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
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- info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
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+ info->reg_ndcr |= NDCR_SPARE_EN;
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+
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+ return 0;
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+}
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+
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+static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
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+{
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+ struct pxa3xx_nand_host *host = info->host[info->cs];
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+ struct mtd_info *mtd = host->mtd;
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+ struct nand_chip *chip = mtd->priv;
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+
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info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
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info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
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info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
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-
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- return 0;
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}
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static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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{
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+ struct platform_device *pdev = info->pdev;
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+ struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
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uint32_t ndcr = nand_readl(info, NDCR);
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/* Set an initial chunk size */
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info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
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info->reg_ndcr = ndcr &
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~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
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+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
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info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
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return 0;
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@@ -1635,10 +1644,7 @@ static int pxa3xx_nand_scan(struct mtd_i
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if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
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goto KEEP_CONFIG;
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- /* Set a default chunk size */
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- info->chunk_size = PAGE_CHUNK_SIZE;
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-
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- ret = pxa3xx_nand_config_flash(info);
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+ ret = pxa3xx_nand_config_ident(info);
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if (ret)
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return ret;
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@@ -1651,7 +1657,6 @@ static int pxa3xx_nand_scan(struct mtd_i
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}
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KEEP_CONFIG:
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- info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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if (info->reg_ndcr & NDCR_DWIDTH_M)
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chip->options |= NAND_BUSWIDTH_16;
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@@ -1736,6 +1741,10 @@ KEEP_CONFIG:
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host->row_addr_cycles = 3;
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else
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host->row_addr_cycles = 2;
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+
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+ if (!pdata->keep_config)
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+ pxa3xx_nand_config_tail(info);
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+
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return nand_scan_tail(mtd);
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}
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