2014-07-12 12:31:47 +00:00
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From 6e74b82aca08a5ecc4d2f0780254468659427e82 Mon Sep 17 00:00:00 2001
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2013-07-20 11:30:26 +00:00
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Fri, 26 Apr 2013 12:03:15 +0200
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2014-07-12 12:31:47 +00:00
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Subject: [PATCH 08/10] MIPS: BCM63XX: wire up the second cpu's irq line
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2013-07-20 11:30:26 +00:00
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2014-07-12 12:31:47 +00:00
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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2013-07-20 11:30:26 +00:00
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---
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2014-01-13 12:13:15 +00:00
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arch/mips/bcm63xx/irq.c | 44 +++++++++++++++++++++++++++++++++++++-------
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1 file changed, 37 insertions(+), 7 deletions(-)
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2013-07-20 11:30:26 +00:00
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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2014-01-13 12:13:15 +00:00
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@@ -102,11 +102,17 @@ static void __internal_irq_mask_##width(
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2013-07-20 11:30:26 +00:00
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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unsigned long flags; \
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+ int cpu; \
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\
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spin_lock_irqsave(&ipic_lock, flags); \
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2014-01-13 12:13:15 +00:00
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- val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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2013-07-20 11:30:26 +00:00
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- val &= ~(1 << bit); \
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2014-01-13 12:13:15 +00:00
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- bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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2013-07-20 11:30:26 +00:00
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+ for_each_present_cpu(cpu) { \
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2014-01-13 12:13:15 +00:00
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+ if (!irq_mask_addr[cpu]) \
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2013-07-20 11:30:26 +00:00
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+ break; \
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+ \
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2014-01-13 12:13:15 +00:00
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+ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
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2013-07-20 11:30:26 +00:00
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+ val &= ~(1 << bit); \
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2014-01-13 12:13:15 +00:00
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+ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
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2013-07-20 11:30:26 +00:00
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+ } \
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spin_unlock_irqrestore(&ipic_lock, flags); \
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} \
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\
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2014-01-13 12:13:15 +00:00
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@@ -116,11 +122,20 @@ static void __internal_irq_unmask_##widt
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2013-07-20 11:30:26 +00:00
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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2014-07-12 12:31:47 +00:00
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unsigned bit = irq & 0x1f; \
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2013-07-20 11:30:26 +00:00
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unsigned long flags; \
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+ int cpu; \
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\
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spin_lock_irqsave(&ipic_lock, flags); \
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2014-01-13 12:13:15 +00:00
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- val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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2014-07-12 12:31:47 +00:00
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- val |= (1 << bit); \
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2014-01-13 12:13:15 +00:00
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- bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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2013-07-20 11:30:26 +00:00
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+ for_each_present_cpu(cpu) { \
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2014-01-13 12:13:15 +00:00
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+ if (!irq_mask_addr[cpu]) \
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2013-07-20 11:30:26 +00:00
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+ break; \
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+ \
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2014-01-13 12:13:15 +00:00
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+ val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
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2013-07-20 11:30:26 +00:00
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+ if (cpu_online(cpu)) \
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2014-07-12 12:31:47 +00:00
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+ val |= (1 << bit); \
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2013-07-20 11:30:26 +00:00
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+ else \
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+ val &= ~(1 << bit); \
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2014-01-13 12:13:15 +00:00
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+ bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
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2013-07-20 11:30:26 +00:00
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+ } \
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spin_unlock_irqrestore(&ipic_lock, flags); \
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}
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2014-01-13 12:13:15 +00:00
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@@ -145,7 +160,10 @@ asmlinkage void plat_irq_dispatch(void)
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2013-07-20 11:30:26 +00:00
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do_IRQ(1);
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if (cause & CAUSEF_IP2)
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dispatch_internal(0);
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- if (!is_ext_irq_cascaded) {
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+ if (is_ext_irq_cascaded) {
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+ if (cause & CAUSEF_IP3)
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+ dispatch_internal(1);
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+ } else {
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if (cause & CAUSEF_IP3)
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do_IRQ(IRQ_EXT_0);
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if (cause & CAUSEF_IP4)
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2014-01-13 12:13:15 +00:00
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@@ -358,6 +376,14 @@ static struct irqaction cpu_ip2_cascade_
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2013-07-20 11:30:26 +00:00
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.flags = IRQF_NO_THREAD,
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};
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+#ifdef CONFIG_SMP
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+static struct irqaction cpu_ip3_cascade_action = {
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+ .handler = no_action,
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+ .name = "cascade_ip3",
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+ .flags = IRQF_NO_THREAD,
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+};
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+#endif
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+
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static struct irqaction cpu_ext_cascade_action = {
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.handler = no_action,
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.name = "cascade_extirq",
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2014-01-13 12:13:15 +00:00
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@@ -494,4 +520,8 @@ void __init arch_init_irq(void)
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2013-07-20 11:30:26 +00:00
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}
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
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+#ifdef CONFIG_SMP
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+ if (is_ext_irq_cascaded)
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+ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
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+#endif
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}
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