564 lines
14 KiB
C
564 lines
14 KiB
C
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/*
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* Low-Level PCI and SB support for BCM47xx
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#include <typedefs.h>
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#include <pcicfg.h>
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#include <bcmdevs.h>
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#include <sbconfig.h>
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#include <sbpci.h>
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#include <osl.h>
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#include <bcmendian.h>
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#include <bcmutils.h>
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#include <sbutils.h>
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#include <bcmnvram.h>
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#include <hndmips.h>
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/* Can free sbpci_init() memory after boot */
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#ifndef linux
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#define __init
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#endif
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/* Emulated configuration space */
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static pci_config_regs sb_config_regs[SB_MAXCORES];
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/* Banned cores */
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static uint16 pci_ban[32] = { 0 };
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static uint pci_banned = 0;
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/* CardBus mode */
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static bool cardbus = FALSE;
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/* Disable PCI host core */
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static bool pci_disabled = FALSE;
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/*
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* Functions for accessing external PCI configuration space
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*/
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/* Assume one-hot slot wiring */
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#define PCI_SLOT_MAX 16
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static uint32
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config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
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{
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uint coreidx;
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sbpciregs_t *regs;
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uint32 addr = 0;
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/* CardBusMode supports only one device */
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if (cardbus && dev > 1)
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return 0;
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coreidx = sb_coreidx(sbh);
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regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
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/* Type 0 transaction */
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if (bus == 1) {
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/* Skip unwired slots */
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if (dev < PCI_SLOT_MAX) {
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/* Slide the PCI window to the appropriate slot */
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W_REG(®s->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
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addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
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(func << 8) | (off & ~3);
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}
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}
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/* Type 1 transaction */
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else {
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W_REG(®s->sbtopci1, SBTOPCI_CFG1);
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addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
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}
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sb_setcoreidx(sbh, coreidx);
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return addr;
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}
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static int
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extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
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{
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uint32 addr, *reg = NULL, val;
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int ret = 0;
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if (pci_disabled ||
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!(addr = config_cmd(sbh, bus, dev, func, off)) ||
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!(reg = (uint32 *) REG_MAP(addr, len)) ||
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BUSPROBE(val, reg))
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val = 0xffffffff;
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val >>= 8 * (off & 3);
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if (len == 4)
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*((uint32 *) buf) = val;
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else if (len == 2)
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*((uint16 *) buf) = (uint16) val;
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else if (len == 1)
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*((uint8 *) buf) = (uint8) val;
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else
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ret = -1;
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if (reg)
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REG_UNMAP(reg);
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return ret;
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}
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static int
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extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
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{
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uint32 addr, *reg = NULL, val;
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int ret = 0;
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if (pci_disabled ||
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!(addr = config_cmd(sbh, bus, dev, func, off)) ||
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!(reg = (uint32 *) REG_MAP(addr, len)) ||
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BUSPROBE(val, reg))
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goto done;
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if (len == 4)
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val = *((uint32 *) buf);
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else if (len == 2) {
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val &= ~(0xffff << (8 * (off & 3)));
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val |= *((uint16 *) buf) << (8 * (off & 3));
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} else if (len == 1) {
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val &= ~(0xff << (8 * (off & 3)));
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val |= *((uint8 *) buf) << (8 * (off & 3));
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} else
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ret = -1;
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W_REG(reg, val);
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done:
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if (reg)
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REG_UNMAP(reg);
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return ret;
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}
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/*
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* Functions for accessing translated SB configuration space
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*/
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static int
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sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
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{
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pci_config_regs *cfg;
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if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
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return -1;
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cfg = &sb_config_regs[dev];
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ASSERT(ISALIGNED(off, len));
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ASSERT(ISALIGNED(buf, len));
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if (len == 4)
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*((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
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else if (len == 2)
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*((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
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else if (len == 1)
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*((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
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else
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return -1;
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return 0;
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}
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static int
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sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
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{
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uint coreidx, n;
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void *regs;
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sbconfig_t *sb;
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pci_config_regs *cfg;
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if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
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return -1;
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cfg = &sb_config_regs[dev];
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ASSERT(ISALIGNED(off, len));
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ASSERT(ISALIGNED(buf, len));
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/* Emulate BAR sizing */
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if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
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len == 4 && *((uint32 *) buf) == ~0) {
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coreidx = sb_coreidx(sbh);
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if ((regs = sb_setcoreidx(sbh, dev))) {
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sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
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/* Highest numbered address match register */
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n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
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if (off == OFFSETOF(pci_config_regs, base[0]))
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cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
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else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
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cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
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else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
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cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
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else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
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cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
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}
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sb_setcoreidx(sbh, coreidx);
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return 0;
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}
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if (len == 4)
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*((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
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else if (len == 2)
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*((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
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else if (len == 1)
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*((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
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else
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return -1;
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return 0;
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}
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int
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sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
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{
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if (bus == 0)
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return sb_read_config(sbh, bus, dev, func, off, buf, len);
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else
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return extpci_read_config(sbh, bus, dev, func, off, buf, len);
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}
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int
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sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
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{
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if (bus == 0)
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return sb_write_config(sbh, bus, dev, func, off, buf, len);
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else
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return extpci_write_config(sbh, bus, dev, func, off, buf, len);
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}
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void
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sbpci_ban(uint16 core)
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{
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if (pci_banned < ARRAYSIZE(pci_ban))
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pci_ban[pci_banned++] = core;
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}
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//#define CT4712_WR 1 /* Workaround for 4712 */
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int __init
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sbpci_init(void *sbh)
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{
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uint chip, chiprev, chippkg, coreidx, host, i;
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uint32 boardflags;
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sbpciregs_t *pci;
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sbconfig_t *sb;
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pci_config_regs *cfg;
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void *regs;
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char varname[8];
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int CT4712_WR;
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uint wlidx = 0;
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uint16 vendor, core;
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uint8 class, subclass, progif;
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uint32 val;
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uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
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uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
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chip = sb_chip(sbh);
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chiprev = sb_chiprev(sbh);
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chippkg = sb_chippkg(sbh);
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coreidx = sb_coreidx(sbh);
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if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0)))
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return -1;
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sb_core_reset(sbh, 0);
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/* In some board, */
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if(nvram_match("boardtype", "bcm94710dev"))
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CT4712_WR = 0;
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else
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CT4712_WR = 1;
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boardflags = (uint32) getintvar(NULL, "boardflags");
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if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
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pci_disabled = TRUE;
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/*
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* The 200-pin BCM4712 package does not bond out PCI. Even when
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* PCI is bonded out, some boards may leave the pins
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* floating.
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*/
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if (((chip == BCM4712_DEVICE_ID) && (chippkg == BCM4712SMALL_PKG_ID)) ||
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(boardflags & BFL_NOPCI) || CT4712_WR)
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pci_disabled = TRUE;
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/*
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* If the PCI core should not be touched (disabled, not bonded
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* out, or pins floating), do not even attempt to access core
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* registers. Otherwise, try to determine if it is in host
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* mode.
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*/
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if (pci_disabled)
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host = 0;
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else
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host = !BUSPROBE(val, &pci->control);
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if (!host) {
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/* Disable PCI interrupts in client mode */
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sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
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W_REG(&sb->sbintvec, 0);
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/* Disable the PCI bridge in client mode */
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sbpci_ban(SB_PCI);
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printf("PCI: Disabled\n");
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} else {
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/* Reset the external PCI bus and enable the clock */
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W_REG(&pci->control, 0x5); /* enable the tristate drivers */
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W_REG(&pci->control, 0xd); /* enable the PCI clock */
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OSL_DELAY(150); /* delay > 100 us */
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W_REG(&pci->control, 0xf); /* deassert PCI reset */
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W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
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OSL_DELAY(1); /* delay 1 us */
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/* Enable CardBusMode */
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cardbus = nvram_match("cardbus", "1");
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if (cardbus) {
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printf("PCI: Enabling CardBus\n");
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/* GPIO 1 resets the CardBus device on bcm94710ap */
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sb_gpioout(sbh, 1, 1);
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sb_gpioouten(sbh, 1, 1);
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W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
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}
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/* 64 MB I/O access window */
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W_REG(&pci->sbtopci0, SBTOPCI_IO);
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/* 64 MB configuration access window */
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W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
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/* 1 GB memory access window */
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W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
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/* Enable PCI bridge BAR0 prefetch and burst */
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val = 6;
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sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
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/* Enable PCI interrupts */
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W_REG(&pci->intmask, PCI_INTA);
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}
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/* Scan the SB bus */
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bzero(sb_config_regs, sizeof(sb_config_regs));
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for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
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cfg->vendor = 0xffff;
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if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
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continue;
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sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
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/* Read ID register and parse vendor and core */
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val = R_REG(&sb->sbidhigh);
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vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
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core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
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|
|
progif = 0;
|
||
|
|
|
||
|
|
/* Check if this core is banned */
|
||
|
|
for (i = 0; i < pci_banned; i++)
|
||
|
|
if (core == pci_ban[i])
|
||
|
|
break;
|
||
|
|
if (i < pci_banned)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
/* Known vendor translations */
|
||
|
|
switch (vendor) {
|
||
|
|
case SB_VEND_BCM:
|
||
|
|
vendor = VENDOR_BROADCOM;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Determine class based on known core codes */
|
||
|
|
switch (core) {
|
||
|
|
case SB_ILINE20:
|
||
|
|
class = PCI_CLASS_NET;
|
||
|
|
subclass = PCI_NET_ETHER;
|
||
|
|
core = BCM47XX_ILINE_ID;
|
||
|
|
break;
|
||
|
|
case SB_ILINE100:
|
||
|
|
class = PCI_CLASS_NET;
|
||
|
|
subclass = PCI_NET_ETHER;
|
||
|
|
core = BCM4610_ILINE_ID;
|
||
|
|
break;
|
||
|
|
case SB_ENET:
|
||
|
|
class = PCI_CLASS_NET;
|
||
|
|
subclass = PCI_NET_ETHER;
|
||
|
|
core = BCM47XX_ENET_ID;
|
||
|
|
break;
|
||
|
|
case SB_SDRAM:
|
||
|
|
case SB_MEMC:
|
||
|
|
class = PCI_CLASS_MEMORY;
|
||
|
|
subclass = PCI_MEMORY_RAM;
|
||
|
|
break;
|
||
|
|
case SB_PCI:
|
||
|
|
class = PCI_CLASS_BRIDGE;
|
||
|
|
subclass = PCI_BRIDGE_PCI;
|
||
|
|
break;
|
||
|
|
case SB_MIPS:
|
||
|
|
case SB_MIPS33:
|
||
|
|
class = PCI_CLASS_CPU;
|
||
|
|
subclass = PCI_CPU_MIPS;
|
||
|
|
break;
|
||
|
|
case SB_CODEC:
|
||
|
|
class = PCI_CLASS_COMM;
|
||
|
|
subclass = PCI_COMM_MODEM;
|
||
|
|
core = BCM47XX_V90_ID;
|
||
|
|
break;
|
||
|
|
case SB_USB:
|
||
|
|
class = PCI_CLASS_SERIAL;
|
||
|
|
subclass = PCI_SERIAL_USB;
|
||
|
|
progif = 0x10; /* OHCI */
|
||
|
|
core = BCM47XX_USB_ID;
|
||
|
|
break;
|
||
|
|
case SB_USB11H:
|
||
|
|
class = PCI_CLASS_SERIAL;
|
||
|
|
subclass = PCI_SERIAL_USB;
|
||
|
|
progif = 0x10; /* OHCI */
|
||
|
|
core = BCM47XX_USBH_ID;
|
||
|
|
break;
|
||
|
|
case SB_USB11D:
|
||
|
|
class = PCI_CLASS_SERIAL;
|
||
|
|
subclass = PCI_SERIAL_USB;
|
||
|
|
core = BCM47XX_USBD_ID;
|
||
|
|
break;
|
||
|
|
case SB_IPSEC:
|
||
|
|
class = PCI_CLASS_CRYPT;
|
||
|
|
subclass = PCI_CRYPT_NETWORK;
|
||
|
|
core = BCM47XX_IPSEC_ID;
|
||
|
|
break;
|
||
|
|
case SB_EXTIF:
|
||
|
|
case SB_CC:
|
||
|
|
class = PCI_CLASS_MEMORY;
|
||
|
|
subclass = PCI_MEMORY_FLASH;
|
||
|
|
break;
|
||
|
|
case SB_D11:
|
||
|
|
class = PCI_CLASS_NET;
|
||
|
|
subclass = PCI_NET_OTHER;
|
||
|
|
/* Let an nvram variable override this */
|
||
|
|
sprintf(varname, "wl%did", wlidx);
|
||
|
|
wlidx++;
|
||
|
|
if ((core = getintvar(NULL, varname)) == 0) {
|
||
|
|
if (chip == BCM4712_DEVICE_ID) {
|
||
|
|
if (chippkg == BCM4712SMALL_PKG_ID)
|
||
|
|
core = BCM4306_D11G_ID;
|
||
|
|
else
|
||
|
|
core = BCM4306_D11DUAL_ID;
|
||
|
|
} else {
|
||
|
|
/* 4310 */
|
||
|
|
core = BCM4310_D11B_ID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
class = subclass = progif = 0xff;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Supported translations */
|
||
|
|
cfg->vendor = htol16(vendor);
|
||
|
|
cfg->device = htol16(core);
|
||
|
|
cfg->rev_id = chiprev;
|
||
|
|
cfg->prog_if = progif;
|
||
|
|
cfg->sub_class = subclass;
|
||
|
|
cfg->base_class = class;
|
||
|
|
cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
|
||
|
|
cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
|
||
|
|
cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
|
||
|
|
cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
|
||
|
|
cfg->base[4] = 0;
|
||
|
|
cfg->base[5] = 0;
|
||
|
|
if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
|
||
|
|
cfg->header_type = PCI_HEADER_BRIDGE;
|
||
|
|
else
|
||
|
|
cfg->header_type = PCI_HEADER_NORMAL;
|
||
|
|
/* Save core interrupt flag */
|
||
|
|
cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
|
||
|
|
/* Default to MIPS shared interrupt 0 */
|
||
|
|
cfg->int_line = 0;
|
||
|
|
/* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
|
||
|
|
if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
|
||
|
|
(regs = sb_setcore(sbh, SB_MIPS33, 0))) {
|
||
|
|
sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
|
||
|
|
val = R_REG(&sb->sbipsflag);
|
||
|
|
for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
|
||
|
|
if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (cfg->int_line > 4)
|
||
|
|
cfg->int_line = 0;
|
||
|
|
}
|
||
|
|
/* Emulated core */
|
||
|
|
*((uint32 *) &cfg->sprom_control) = 0xffffffff;
|
||
|
|
}
|
||
|
|
|
||
|
|
sb_setcoreidx(sbh, coreidx);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
sbpci_check(void *sbh)
|
||
|
|
{
|
||
|
|
uint coreidx;
|
||
|
|
sbpciregs_t *pci;
|
||
|
|
uint32 sbtopci1;
|
||
|
|
uint32 buf[64], *ptr, i;
|
||
|
|
ulong pa;
|
||
|
|
volatile uint j;
|
||
|
|
|
||
|
|
coreidx = sb_coreidx(sbh);
|
||
|
|
pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
|
||
|
|
|
||
|
|
/* Clear the test array */
|
||
|
|
pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
|
||
|
|
ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
|
||
|
|
memset(ptr, 0, sizeof(buf));
|
||
|
|
|
||
|
|
/* Point PCI window 1 to memory */
|
||
|
|
sbtopci1 = R_REG(&pci->sbtopci1);
|
||
|
|
W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
|
||
|
|
|
||
|
|
/* Fill the test array via PCI window 1 */
|
||
|
|
ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
|
||
|
|
for (i = 0; i < ARRAYSIZE(buf); i++) {
|
||
|
|
for (j = 0; j < 2; j++);
|
||
|
|
W_REG(&ptr[i], i);
|
||
|
|
}
|
||
|
|
REG_UNMAP(ptr);
|
||
|
|
|
||
|
|
/* Restore PCI window 1 */
|
||
|
|
W_REG(&pci->sbtopci1, sbtopci1);
|
||
|
|
|
||
|
|
/* Check the test array */
|
||
|
|
DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
|
||
|
|
ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
|
||
|
|
for (i = 0; i < ARRAYSIZE(buf); i++) {
|
||
|
|
if (ptr[i] != i)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Change the clock if the test fails */
|
||
|
|
if (i < ARRAYSIZE(buf)) {
|
||
|
|
uint32 req, cur;
|
||
|
|
|
||
|
|
cur = sb_clock(sbh);
|
||
|
|
printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
|
||
|
|
for (req = 104000000; req < 176000000; req += 4000000) {
|
||
|
|
printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
|
||
|
|
/* This will only reset if the clocks are valid and have changed */
|
||
|
|
sb_mips_setclock(sbh, req, 0, 0);
|
||
|
|
}
|
||
|
|
/* Should not reach here */
|
||
|
|
ASSERT(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
sb_setcoreidx(sbh, coreidx);
|
||
|
|
}
|