102 lines
2.8 KiB
Diff
102 lines
2.8 KiB
Diff
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From 78c8c8dc7e27c4502504cb4daa07bc9762f54de9 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 14 Nov 2013 18:25:33 -0300
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Subject: [PATCH 147/203] mtd: nand: pxa3xx: Split prepare_command_pool() in
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two stages
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This commit splits the prepare_command_pool() function into two
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stages: prepare_start_command() / prepare_set_command().
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This is a preparation patch without any functionality changes,
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and is meant to allow support for multiple page reading/writing
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operations.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 44 ++++++++++++++++++++++++------------------
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1 file changed, 25 insertions(+), 19 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -607,18 +607,8 @@ static void set_command_address(struct p
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}
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}
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-static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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- uint16_t column, int page_addr)
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+static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
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{
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- int addr_cycle, exec_cmd;
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- struct pxa3xx_nand_host *host;
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- struct mtd_info *mtd;
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-
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- host = info->host[info->cs];
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- mtd = host->mtd;
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- addr_cycle = 0;
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- exec_cmd = 1;
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-
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/* reset data and oob column point to handle data */
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info->buf_start = 0;
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info->buf_count = 0;
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@@ -627,10 +617,6 @@ static int prepare_command_pool(struct p
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info->use_spare = 1;
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info->retcode = ERR_NONE;
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info->ndcb3 = 0;
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- if (info->cs != 0)
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- info->ndcb0 = NDCB0_CSEL;
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- else
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- info->ndcb0 = 0;
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switch (command) {
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case NAND_CMD_READ0:
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@@ -642,14 +628,32 @@ static int prepare_command_pool(struct p
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case NAND_CMD_PARAM:
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info->use_spare = 0;
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break;
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- case NAND_CMD_SEQIN:
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- exec_cmd = 0;
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- break;
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default:
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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break;
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}
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+}
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+
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+static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
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+ uint16_t column, int page_addr)
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+{
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+ int addr_cycle, exec_cmd;
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+ struct pxa3xx_nand_host *host;
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+ struct mtd_info *mtd;
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+
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+ host = info->host[info->cs];
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+ mtd = host->mtd;
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+ addr_cycle = 0;
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+ exec_cmd = 1;
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+
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+ if (info->cs != 0)
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+ info->ndcb0 = NDCB0_CSEL;
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+ else
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+ info->ndcb0 = 0;
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+
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+ if (command == NAND_CMD_SEQIN)
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+ exec_cmd = 0;
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addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
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+ host->col_addr_cycles);
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@@ -784,8 +788,10 @@ static void pxa3xx_nand_cmdfunc(struct m
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nand_writel(info, NDTR1CS0, info->ndtr1cs0);
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}
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+ prepare_start_command(info, command);
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+
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info->state = STATE_PREPARED;
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- exec_cmd = prepare_command_pool(info, command, column, page_addr);
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+ exec_cmd = prepare_set_command(info, command, column, page_addr);
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if (exec_cmd) {
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init_completion(&info->cmd_complete);
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init_completion(&info->dev_ready);
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