43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
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From 190ae222ef6ded27021620afdc3f5a36861d3625 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Tue, 17 Jan 2017 17:32:38 +0800
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Subject: [PATCH 07/13] arm: dts: ls1021a: share all MSIs
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Cherry-pick patchwork patch.
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In order to maximize the use of MSI, a PCIe controller will share
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all MSI controllers. The patch changes msi-parent to refer to all
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MSI controller dts nodes.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
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index a2a3e8e..bf4ffeb 100644
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--- a/arch/arm/boot/dts/ls1021a.dtsi
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+++ b/arch/arm/boot/dts/ls1021a.dtsi
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@@ -568,7 +568,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi1>;
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+ msi-parent = <&msi1>, <&msi2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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@@ -591,7 +591,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi2>;
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+ msi-parent = <&msi1>, <&msi2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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--
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2.1.0.27.g96db324
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