34 lines
1.1 KiB
Diff
34 lines
1.1 KiB
Diff
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From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001
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From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
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Date: Mon, 13 Jun 2016 17:29:59 +0530
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Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings
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DDR timigs displayed for LS1012A were half of true value.
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Updated DDR value to 1000 MT/s.
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Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
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---
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.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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index 63e5bed..a4dde5b 100644
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--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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@@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info)
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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- if (ver == SVR_LS1012)
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+ if (ver == SVR_LS1012){
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sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
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-
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+ sys_info->freq_ddrbus *=2;
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+ }
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#define HWA_CGA_M1_CLK_SEL 0xe0000000
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#define HWA_CGA_M1_CLK_SHIFT 29
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#ifdef CONFIG_SYS_DPAA_FMAN
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--
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1.7.9.5
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