49 lines
1.5 KiB
Diff
49 lines
1.5 KiB
Diff
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From fe0ffa96c83e318d6b99fe31b5d121bdb05247f7 Mon Sep 17 00:00:00 2001
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From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Date: Tue, 24 May 2016 14:52:59 +0530
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Subject: [PATCH 44/93] armv8: fsl-layerscape: Add support of GPIO structure
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[context adjustment]
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Layerscape supports GPIO registers to conrol GPIO singals.
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Add support of GPIO structure to enable GPIO access.
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
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---
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.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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index a264f9a..58c7205 100644
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--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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@@ -44,6 +44,7 @@
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#define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
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#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
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#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
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+#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
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#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
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@@ -650,6 +651,15 @@ struct ccsr_cci400 {
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u8 res_e004[0x10000 - 0xe004];
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};
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+typedef struct ccsr_gpio {
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+ u32 gpdir;
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+ u32 gpodr;
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+ u32 gpdat;
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+ u32 gpier;
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+ u32 gpimr;
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+ u32 gpicr;
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+} ccsr_gpio_t;
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+
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/* MMU 500 */
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#define SMMU_SCR0 (SMMU_BASE + 0x0)
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#define SMMU_SCR1 (SMMU_BASE + 0x4)
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--
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1.7.9.5
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