46 lines
1.6 KiB
Diff
46 lines
1.6 KiB
Diff
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From ae717a9744a3e18f2ed0a6aa44e279c89ad5052c Mon Sep 17 00:00:00 2001
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From: Gabriele Paoloni <gabriele.paoloni@huawei.com>
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Date: Sat, 16 Apr 2016 12:03:39 +0100
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Subject: [PATCH 59/70] PCI: designware: Remove incorrect RC memory base/limit
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configuration
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Currently dw_pcie_setup_rc() configures memory base and memory limit in the
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type1 configuration header for the root complex. In doing so it uses the
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CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
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This is wrong and it is useless since the configuration is overwritten
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later on when pci_bus_assign_resources() is called.
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Remove this configuration from dw_pcie_setup_rc().
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Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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---
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drivers/pci/host/pcie-designware.c | 8 --------
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1 file changed, 8 deletions(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -708,8 +708,6 @@ static struct pci_ops dw_pcie_ops = {
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void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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u32 val;
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- u32 membase;
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- u32 memlimit;
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/* set the number of lanes */
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dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
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@@ -768,12 +766,6 @@ void dw_pcie_setup_rc(struct pcie_port *
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val |= 0x00010100;
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dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
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- /* setup memory base, memory limit */
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- membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
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- memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
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- val = memlimit | membase;
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- dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
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-
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/* setup command register */
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dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
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val &= 0xffff0000;
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