95 lines
4 KiB
Diff
95 lines
4 KiB
Diff
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From b1f4d42406261ed1ddffbbf0582ebbfaf6c0a73b Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Wed, 16 Mar 2016 12:24:57 -0700
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Subject: [PATCH 395/423] dmaengine: bcm2835: add additional defines for
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DMA-registers
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Add additional defines describing the DMA registers
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as well as adding some more documentation to those registers.
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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---
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drivers/dma/bcm2835-dma.c | 57 ++++++++++++++++++++++++++++++++++++++++-------
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1 file changed, 49 insertions(+), 8 deletions(-)
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--- a/drivers/dma/bcm2835-dma.c
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+++ b/drivers/dma/bcm2835-dma.c
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@@ -97,26 +97,67 @@ struct bcm2835_desc {
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#define BCM2835_DMA_CS 0x00
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#define BCM2835_DMA_ADDR 0x04
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+#define BCM2835_DMA_TI 0x08
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#define BCM2835_DMA_SOURCE_AD 0x0c
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#define BCM2835_DMA_DEST_AD 0x10
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-#define BCM2835_DMA_NEXTCB 0x1C
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+#define BCM2835_DMA_LEN 0x14
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+#define BCM2835_DMA_STRIDE 0x18
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+#define BCM2835_DMA_NEXTCB 0x1c
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+#define BCM2835_DMA_DEBUG 0x20
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/* DMA CS Control and Status bits */
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-#define BCM2835_DMA_ACTIVE BIT(0)
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-#define BCM2835_DMA_INT BIT(2)
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+#define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */
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+#define BCM2835_DMA_END BIT(1) /* current CB has ended */
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+#define BCM2835_DMA_INT BIT(2) /* interrupt status */
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+#define BCM2835_DMA_DREQ BIT(3) /* DREQ state */
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#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
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#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
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-#define BCM2835_DMA_ERR BIT(8)
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+#define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
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+ * AXI-write to ack
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+ */
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+#define BCM2835_DMA_ERR BIT(8)
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+#define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
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+#define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
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+/* current value of TI.BCM2835_DMA_WAIT_RESP */
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+#define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
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+#define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */
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#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
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#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
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+/* Transfer information bits - also bcm2835_cb.info field */
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#define BCM2835_DMA_INT_EN BIT(0)
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+#define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */
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+#define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */
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#define BCM2835_DMA_D_INC BIT(4)
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-#define BCM2835_DMA_D_DREQ BIT(6)
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+#define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */
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+#define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */
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+#define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */
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#define BCM2835_DMA_S_INC BIT(8)
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-#define BCM2835_DMA_S_DREQ BIT(10)
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+#define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */
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+#define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */
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+#define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */
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+#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
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+#define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
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+#define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */
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+#define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
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-#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
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+/* debug register bits */
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+#define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0)
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+#define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1)
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+#define BCM2835_DMA_DEBUG_READ_ERR BIT(2)
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+#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
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+#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
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+#define BCM2835_DMA_DEBUG_ID_SHIFT 16
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+#define BCM2835_DMA_DEBUG_ID_BITS 9
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+#define BCM2835_DMA_DEBUG_STATE_SHIFT 16
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+#define BCM2835_DMA_DEBUG_STATE_BITS 9
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+#define BCM2835_DMA_DEBUG_VERSION_SHIFT 25
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+#define BCM2835_DMA_DEBUG_VERSION_BITS 3
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+#define BCM2835_DMA_DEBUG_LITE BIT(28)
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+
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+/* shared registers for all dma channels */
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+#define BCM2835_DMA_INT_STATUS 0xfe0
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+#define BCM2835_DMA_ENABLE 0xff0
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#define BCM2835_DMA_DATA_TYPE_S8 1
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#define BCM2835_DMA_DATA_TYPE_S16 2
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