72 lines
2.1 KiB
Diff
72 lines
2.1 KiB
Diff
|
From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Kristian Evensen <kristian.evensen@gmail.com>
|
||
|
|
Date: Mon, 30 Apr 2018 14:38:01 +0200
|
||
|
|
Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
|
||
|
|
|
||
|
|
---
|
||
|
|
drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
|
||
|
|
1 file changed, 20 insertions(+)
|
||
|
|
|
||
|
|
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
|
||
|
|
index 721a2a1c9..0cb1cea53 100644
|
||
|
|
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
|
||
|
|
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
|
||
|
|
@@ -22,6 +22,8 @@
|
||
|
|
#include <linux/of_address.h>
|
||
|
|
#include <linux/phy/phy.h>
|
||
|
|
#include <linux/platform_device.h>
|
||
|
|
+#include <linux/mfd/syscon.h>
|
||
|
|
+#include <linux/regmap.h>
|
||
|
|
|
||
|
|
/* version V1 sub-banks offset base address */
|
||
|
|
/* banks shared by multiple phys */
|
||
|
|
@@ -259,6 +261,9 @@
|
||
|
|
#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
|
||
|
|
#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
|
||
|
|
|
||
|
|
+#define HIF_SYSCFG1 0x14
|
||
|
|
+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20)
|
||
|
|
+
|
||
|
|
enum mtk_phy_version {
|
||
|
|
MTK_PHY_V1 = 1,
|
||
|
|
MTK_PHY_V2,
|
||
|
|
@@ -302,6 +307,7 @@ struct mtk_tphy {
|
||
|
|
struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
|
||
|
|
const struct mtk_phy_pdata *pdata;
|
||
|
|
struct mtk_phy_instance **phys;
|
||
|
|
+ struct regmap *hif;
|
||
|
|
int nphys;
|
||
|
|
};
|
||
|
|
|
||
|
|
@@ -594,6 +600,10 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
|
||
|
|
if (tphy->pdata->version != MTK_PHY_V1)
|
||
|
|
return;
|
||
|
|
|
||
|
|
+ if (tphy->hif)
|
||
|
|
+ regmap_update_bits(tphy->hif, HIF_SYSCFG1,
|
||
|
|
+ HIF_SYSCFG1_PHY2_MASK, 0);
|
||
|
|
+
|
||
|
|
tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
|
||
|
|
tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
|
||
|
|
tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
|
||
|
|
@@ -1008,6 +1018,16 @@ static int mtk_tphy_probe(struct platform_device *pdev)
|
||
|
|
tphy->u3phya_ref = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
+ if (of_find_property(np, "mediatek,phy-switch", NULL)) {
|
||
|
|
+ tphy->hif = syscon_regmap_lookup_by_phandle(np,
|
||
|
|
+ "mediatek,phy-switch");
|
||
|
|
+ if (IS_ERR(tphy->hif)) {
|
||
|
|
+ dev_err(&pdev->dev,
|
||
|
|
+ "missing \"mediatek,phy-switch\" phandle\n");
|
||
|
|
+ return PTR_ERR(tphy->hif);
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
port = 0;
|
||
|
|
for_each_child_of_node(np, child_np) {
|
||
|
|
struct mtk_phy_instance *instance;
|
||
|
|
--
|
||
|
|
2.14.1
|
||
|
|
|