layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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From 2f3ea65dc8909cbf4116bd74b3dea8d25749508f Mon Sep 17 00:00:00 2001
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From: Zhao Qiang <qiang.zhao@nxp.com>
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Date: Wed, 23 Nov 2016 11:29:45 +0800
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Subject: [PATCH 235/238] pci/layerscape: fix pci lut offset issue
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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drivers/pci/host/pci-layerscape.c | 13 ++++---------
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1 file changed, 4 insertions(+), 9 deletions(-)
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--- a/drivers/pci/host/pci-layerscape.c
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+++ b/drivers/pci/host/pci-layerscape.c
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2017-01-06 12:53:27 +00:00
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@@ -158,16 +158,11 @@ static void ls1021_pcie_host_init(struct
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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static int ls_pcie_link_up(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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- u32 state, offset;
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2017-01-06 12:53:27 +00:00
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+ u32 state;
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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- if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL))
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- offset = 0x407fc;
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- else
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- offset = PCIE_LUT_DBG;
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2017-01-06 12:53:27 +00:00
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-
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layerscape: add ls2088ardb device support
The QorIQ LS2088A processor is built on the Layerscape
architecture combining eight ARM A72 processor cores
with advanced, high-performance datapath acceleration
and network, peripheral interfaces required for
networking, telecom, wireless infrastructure, aerospace
applications and general-purpose embedded applications.
Features summary:
- Eight 64-bit ARM v8 Cortex-A72 CPUs
- Two 64-bit DDR4 SDRAM memory controller with ECC
- One 32-bit DDR3 SDRAM memory controller with ECC
- Data path acceleration architecture 2.0 (DPAA2)
- Ethernet interfaces
- IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
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- state = (ioread32(pcie->lut + offset) >>
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- pcie->drvdata->ltssm_shift) &
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- LTSSM_STATE_MASK;
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+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
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+ pcie->drvdata->ltssm_shift) &
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+ LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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