96 lines
2.6 KiB
Diff
96 lines
2.6 KiB
Diff
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From ff0b5fdb65bc7f10af7e83bb0919cb6bec2dc624 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Mon, 23 Dec 2013 00:32:35 -0300
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Subject: [PATCH] ARM: sunxi: add PLL4 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
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device trees. PLL4 is compatible with PLL1.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
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arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
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arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
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arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
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4 files changed, 28 insertions(+)
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diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
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index 0bf70ee..1d6346c 100644
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--- a/arch/arm/boot/dts/sun4i-a10.dtsi
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+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
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@@ -70,6 +70,13 @@
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clocks = <&osc24M>;
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};
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+ pll4: pll4@01c20018 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-pll1-clk";
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+ reg = <0x01c20018 0x4>;
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+ clocks = <&osc24M>;
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+ };
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+
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
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index 924a2c1..64d6d75 100644
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--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
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@@ -67,6 +67,13 @@
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clocks = <&osc24M>;
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};
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+ pll4: pll4@01c20018 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-pll1-clk";
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+ reg = <0x01c20018 0x4>;
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+ clocks = <&osc24M>;
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+ };
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+
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
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index 1ccd75d..2c355c8 100644
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--- a/arch/arm/boot/dts/sun5i-a13.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
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@@ -67,6 +67,13 @@
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clocks = <&osc24M>;
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};
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+ pll4: pll4@01c20018 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-pll1-clk";
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+ reg = <0x01c20018 0x4>;
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+ clocks = <&osc24M>;
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+ };
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+
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
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index c74147a..18144f0 100644
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -66,6 +66,13 @@
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clocks = <&osc24M>;
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};
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+ pll4: pll4@01c20018 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-pll1-clk";
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+ reg = <0x01c20018 0x4>;
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+ clocks = <&osc24M>;
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+ };
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+
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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--
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1.8.5.1
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