2016-02-15 18:45:22 +00:00
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/dts-v1/;
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2016-05-09 06:32:52 +00:00
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#include "mt7620a.dtsi"
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2016-02-15 18:45:22 +00:00
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2017-07-29 02:14:07 +00:00
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#include <dt-bindings/gpio/gpio.h>
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2016-11-11 21:43:08 +00:00
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#include <dt-bindings/input/input.h>
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2016-02-15 18:45:22 +00:00
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/ {
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2017-07-29 02:14:07 +00:00
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compatible = "phicomm,psg1208", "ralink,mt7620a-soc";
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2016-02-15 18:45:22 +00:00
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model = "Phicomm PSG1208";
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2018-07-16 08:27:22 +00:00
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aliases {
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2018-08-28 04:54:27 +00:00
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led-boot = &led_wps;
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led-failsafe = &led_wps;
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led-running = &led_wps;
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led-upgrade = &led_wps;
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2018-07-16 08:27:22 +00:00
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};
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2016-02-15 18:45:22 +00:00
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gpio-leds {
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compatible = "gpio-leds";
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2018-07-16 08:27:22 +00:00
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led_wps: wps {
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2016-02-15 18:45:22 +00:00
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label = "psg1208:white:wps";
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2017-07-29 02:14:07 +00:00
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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2016-02-15 18:45:22 +00:00
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};
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wlan {
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label = "psg1208:white:wlan2g";
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2017-07-29 02:14:07 +00:00
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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2016-02-15 18:45:22 +00:00
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};
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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2017-07-29 02:14:07 +00:00
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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2016-11-11 21:43:08 +00:00
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linux,code = <KEY_RESTART>;
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2016-02-15 18:45:22 +00:00
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};
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};
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};
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2016-05-10 10:41:46 +00:00
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&gpio1 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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compatible = "jedec,spi-nor";
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2016-05-14 17:22:08 +00:00
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reg = <0>;
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2016-05-10 10:41:46 +00:00
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spi-max-frequency = <10000000>;
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2018-08-01 20:32:34 +00:00
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@20000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@30000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@40000 {
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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2016-05-10 10:41:46 +00:00
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};
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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2017-03-05 07:53:40 +00:00
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ralink,group = "i2c", "spi refclk", "wled";
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2016-05-10 10:41:46 +00:00
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ralink,function = "gpio";
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&ephy_pins>;
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mtd-mac-address = <&factory 0x4>;
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mediatek,portmap = "llllw";
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};
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&pcie {
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status = "okay";
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2018-07-21 14:19:46 +00:00
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};
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2016-05-10 10:41:46 +00:00
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2018-07-21 14:19:46 +00:00
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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2016-05-10 10:41:46 +00:00
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};
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0>;
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};
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