47 lines
1.4 KiB
Diff
47 lines
1.4 KiB
Diff
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From 37258bc8fe832e4c681593a864686f627f6d3455 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Tue, 10 Jun 2014 13:09:01 -0500
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Subject: [PATCH 145/182] phy: qcom: Add device tree bindings information
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Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
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the IPQ806x family of SoCs.
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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Documentation/devicetree/bindings/phy/qcom-phy.txt | 23 ++++++++++++++++++++
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1 file changed, 23 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/qcom-phy.txt
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diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt
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new file mode 100644
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index 0000000..76bfbd0
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
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@@ -0,0 +1,23 @@
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+Qualcomm IPQ806x SATA PHY Controller
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+------------------------------------
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+
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+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
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+Each SATA PHY controller should have its own node.
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+
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+Required properties:
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+- compatible: compatible list, contains "qcom,ipq806x-sata-phy"
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+- reg: offset and length of the SATA PHY register set;
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+- #phy-cells: must be zero
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+- clocks: must be exactly one entry
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+- clock-names: must be "cfg"
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+
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+Example:
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+ sata_phy: sata-phy@1b400000 {
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+ compatible = "qcom,ipq806x-sata-phy";
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+ reg = <0x1b400000 0x200>;
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+
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+ clocks = <&gcc SATA_PHY_CFG_CLK>;
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+ clock-names = "cfg";
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+
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+ #phy-cells = <0>;
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+ };
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--
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1.7.10.4
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