77 lines
2.5 KiB
Diff
77 lines
2.5 KiB
Diff
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Fri, 27 Jul 2018 12:39:01 +0200
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Subject: [PATCH] Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe
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erratum"
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This reverts commit 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175.
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Enabling ExternalSync caused a regression for BCM4718A1 (used e.g. in
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Netgear E3000 and ASUS RT-N16): it simply hangs during PCIe
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initialization. It's likely that BCM4717A1 is also affected.
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I didn't notice that earlier as the only BCM47XX devices with PCIe I
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own are:
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1) BCM4706 with 2 x 14e4:4331
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2) BCM4706 with 14e4:4360 and 14e4:4331
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it appears that BCM4706 is unaffected.
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While BCM5300X-ES300-RDS.pdf seems to document that erratum and its
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workarounds (according to quotes provided by Tokunori) it seems not even
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Broadcom follows them.
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According to the provided info Broadcom should define CONF7_ES in their
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SDK's mipsinc.h and implement workaround in the si_mips_init(). Checking
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both didn't reveal such code. It *could* mean Broadcom also had some
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problems with the given workaround.
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Reported-by: Michael Marley <michael@michaelmarley.com>
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Cc: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
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Cc: Paul Burton <paul.burton@mips.com>
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Cc: Hauke Mehrtens <hauke@hauke-m.de>
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Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
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Cc: stable@vger.kernel.org
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Cc: James Hogan <jhogan@kernel.org>
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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arch/mips/bcm47xx/setup.c | 6 ------
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arch/mips/include/asm/mipsregs.h | 3 ---
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2 files changed, 9 deletions(-)
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--- a/arch/mips/bcm47xx/setup.c
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+++ b/arch/mips/bcm47xx/setup.c
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@@ -212,12 +212,6 @@ static int __init bcm47xx_cpu_fixes(void
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*/
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if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
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cpu_wait = NULL;
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-
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- /*
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- * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
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- * Enable ExternalSync for sync instruction to take effect
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- */
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- set_c0_config7(MIPS_CONF7_ES);
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break;
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#endif
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}
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--- a/arch/mips/include/asm/mipsregs.h
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+++ b/arch/mips/include/asm/mipsregs.h
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@@ -680,8 +680,6 @@
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#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
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#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
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-/* ExternalSync */
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-#define MIPS_CONF7_ES (_ULCAST_(1) << 8)
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#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
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#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
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@@ -2747,7 +2745,6 @@ __BUILD_SET_C0(status)
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__BUILD_SET_C0(cause)
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__BUILD_SET_C0(config)
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__BUILD_SET_C0(config5)
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-__BUILD_SET_C0(config7)
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__BUILD_SET_C0(intcontrol)
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__BUILD_SET_C0(intctl)
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__BUILD_SET_C0(srsmap)
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