65 lines
2.5 KiB
Diff
65 lines
2.5 KiB
Diff
|
From 4a1990ee249df257848f9583cef71478e3411c3e Mon Sep 17 00:00:00 2001
|
||
|
|
From: Sean Wang <sean.wang@mediatek.com>
|
||
|
|
Date: Thu, 28 Dec 2017 11:24:45 +0800
|
||
|
|
Subject: [PATCH 201/224] dt-bindings: clock: mediatek: add missing required
|
||
|
|
#reset-cells
|
||
|
|
|
||
|
|
All ethsys, pciesys and ssusbsys internally include reset controller, so
|
||
|
|
explicitly add back these missing cell definitions to related bindings
|
||
|
|
and examples.
|
||
|
|
|
||
|
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||
|
|
Cc: Rob Herring <robh@kernel.org>
|
||
|
|
Cc: Michael Turquette <mturquette@baylibre.com>
|
||
|
|
Cc: Stephen Boyd <sboyd@codeaurora.org>
|
||
|
|
Cc: linux-clk@vger.kernel.org
|
||
|
|
Reviewed-by: Rob Herring <robh@kernel.org>
|
||
|
|
---
|
||
|
|
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
|
||
|
|
Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++
|
||
|
|
Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
|
||
|
|
3 files changed, 5 insertions(+)
|
||
|
|
|
||
|
|
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
||
|
|
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
||
|
|
@@ -9,6 +9,7 @@ Required Properties:
|
||
|
|
- "mediatek,mt2701-ethsys", "syscon"
|
||
|
|
- "mediatek,mt7622-ethsys", "syscon"
|
||
|
|
- #clock-cells: Must be 1
|
||
|
|
+- #reset-cells: Must be 1
|
||
|
|
|
||
|
|
The ethsys controller uses the common clk binding from
|
||
|
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||
|
|
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
|
||
|
|
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
|
||
|
|
@@ -8,6 +8,7 @@ Required Properties:
|
||
|
|
- compatible: Should be:
|
||
|
|
- "mediatek,mt7622-pciesys", "syscon"
|
||
|
|
- #clock-cells: Must be 1
|
||
|
|
+- #reset-cells: Must be 1
|
||
|
|
|
||
|
|
The PCIESYS controller uses the common clk binding from
|
||
|
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||
|
|
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
|
||
|
|
compatible = "mediatek,mt7622-pciesys", "syscon";
|
||
|
|
reg = <0 0x1a100800 0 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
+ #reset-cells = <1>;
|
||
|
|
};
|
||
|
|
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
|
||
|
|
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
|
||
|
|
@@ -8,6 +8,7 @@ Required Properties:
|
||
|
|
- compatible: Should be:
|
||
|
|
- "mediatek,mt7622-ssusbsys", "syscon"
|
||
|
|
- #clock-cells: Must be 1
|
||
|
|
+- #reset-cells: Must be 1
|
||
|
|
|
||
|
|
The SSUSBSYS controller uses the common clk binding from
|
||
|
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||
|
|
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
|
||
|
|
compatible = "mediatek,mt7622-ssusbsys", "syscon";
|
||
|
|
reg = <0 0x1a000000 0 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
+ #reset-cells = <1>;
|
||
|
|
};
|