60 lines
2 KiB
Diff
60 lines
2 KiB
Diff
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From 6bbda039fe5e9d1b3c04f4f0dd8479a2c102d28e Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Mon, 12 Aug 2013 14:14:50 -0300
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Subject: [PATCH 117/203] mtd: nand: pxa3xx: Support command buffer #3
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Some newer controllers support a fourth command buffer. This additional
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command buffer allows to set an arbitrary length count, using the
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NDCB3.NDLENCNT field, to perform non-standard length operations
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such as the ONFI parameter page read.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -197,6 +197,7 @@ struct pxa3xx_nand_info {
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uint32_t ndcb0;
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uint32_t ndcb1;
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uint32_t ndcb2;
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+ uint32_t ndcb3;
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};
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static bool use_dma = 1;
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@@ -493,9 +494,22 @@ static irqreturn_t pxa3xx_nand_irq(int i
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nand_writel(info, NDSR, NDSR_WRCMDREQ);
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status &= ~NDSR_WRCMDREQ;
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info->state = STATE_CMD_HANDLE;
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+
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+ /*
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+ * Command buffer registers NDCB{0-2} (and optionally NDCB3)
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+ * must be loaded by writing directly either 12 or 16
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+ * bytes directly to NDCB0, four bytes at a time.
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+ *
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+ * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
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+ * but each NDCBx register can be read.
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+ */
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nand_writel(info, NDCB0, info->ndcb0);
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nand_writel(info, NDCB0, info->ndcb1);
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nand_writel(info, NDCB0, info->ndcb2);
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+
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+ /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
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+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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+ nand_writel(info, NDCB0, info->ndcb3);
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}
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/* clear NDSR to let the controller exit the IRQ */
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@@ -554,6 +568,7 @@ static int prepare_command_pool(struct p
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default:
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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+ info->ndcb3 = 0;
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break;
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}
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