247 lines
7.9 KiB
C
247 lines
7.9 KiB
C
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/*
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* Driver for sunxi SD/MMC host controllers
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* (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
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* (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
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* (C) Copyright 2013-2013 O2S GmbH <www.o2s.ch>
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* (C) Copyright 2013-2013 David Lanzend<EFBFBD>rfer <david.lanzendoerfer@o2s.ch>
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* (C) Copyright 2013-2013 Hans de Goede <hdegoede@redhat.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SUNXI_MCI_H__
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#define __SUNXI_MCI_H__
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/* register offset define */
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#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
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#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
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#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
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#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
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#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
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#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
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#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
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#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
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#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
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#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
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#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
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#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
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#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
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#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
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#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
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#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
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#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
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#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
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#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
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#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
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#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
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#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
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#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
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#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
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#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
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#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
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#define SDXC_REG_CHDA (0x90)
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#define SDXC_REG_CBDA (0x94)
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#define mci_readl(host, reg) \
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__raw_readl((host)->reg_base + SDXC_##reg)
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#define mci_writel(host, reg, value) \
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__raw_writel((value), (host)->reg_base + SDXC_##reg)
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/* global control register bits */
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#define SDXC_SoftReset BIT(0)
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#define SDXC_FIFOReset BIT(1)
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#define SDXC_DMAReset BIT(2)
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#define SDXC_HWReset (SDXC_SoftReset|SDXC_FIFOReset|SDXC_DMAReset)
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#define SDXC_INTEnb BIT(4)
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#define SDXC_DMAEnb BIT(5)
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#define SDXC_DebounceEnb BIT(8)
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#define SDXC_PosedgeLatchData BIT(9)
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#define SDXC_DDR_MODE BIT(10)
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#define SDXC_MemAccessDone BIT(29)
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#define SDXC_AccessDoneDirect BIT(30)
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#define SDXC_ACCESS_BY_AHB BIT(31)
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#define SDXC_ACCESS_BY_DMA (0U << 31)
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/* clock control bits */
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#define SDXC_CardClkOn BIT(16)
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#define SDXC_LowPowerOn BIT(17)
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/* bus width */
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#define SDXC_WIDTH1 (0)
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#define SDXC_WIDTH4 (1)
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#define SDXC_WIDTH8 (2)
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/* smc command bits */
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#define SDXC_RspExp BIT(6)
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#define SDXC_LongRsp BIT(7)
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#define SDXC_CheckRspCRC BIT(8)
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#define SDXC_DataExp BIT(9)
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#define SDXC_Write BIT(10)
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#define SDXC_Seqmod BIT(11)
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#define SDXC_SendAutoStop BIT(12)
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#define SDXC_WaitPreOver BIT(13)
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#define SDXC_StopAbortCMD BIT(14)
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#define SDXC_SendInitSeq BIT(15)
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#define SDXC_UPCLKOnly BIT(21)
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#define SDXC_RdCEATADev BIT(22)
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#define SDXC_CCSExp BIT(23)
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#define SDXC_EnbBoot BIT(24)
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#define SDXC_AltBootOpt BIT(25)
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#define SDXC_BootACKExp BIT(26)
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#define SDXC_BootAbort BIT(27)
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#define SDXC_VolSwitch BIT(28)
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#define SDXC_UseHoldReg BIT(29)
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#define SDXC_Start BIT(31)
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/* interrupt bits */
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#define SDXC_RespErr BIT(1)
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#define SDXC_CmdDone BIT(2)
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#define SDXC_DataOver BIT(3)
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#define SDXC_TxDataReq BIT(4)
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#define SDXC_RxDataReq BIT(5)
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#define SDXC_RespCRCErr BIT(6)
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#define SDXC_DataCRCErr BIT(7)
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#define SDXC_RespTimeout BIT(8)
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#define SDXC_DataTimeout BIT(9)
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#define SDXC_VolChgDone BIT(10)
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#define SDXC_FIFORunErr BIT(11)
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#define SDXC_HardWLocked BIT(12)
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#define SDXC_StartBitErr BIT(13)
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#define SDXC_AutoCMDDone BIT(14)
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#define SDXC_EndBitErr BIT(15)
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#define SDXC_SDIOInt BIT(16)
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#define SDXC_CardInsert BIT(30)
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#define SDXC_CardRemove BIT(31)
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#define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | \
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SDXC_DataCRCErr | SDXC_RespTimeout | \
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SDXC_DataTimeout | SDXC_FIFORunErr | \
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SDXC_HardWLocked | SDXC_StartBitErr | \
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SDXC_EndBitErr) /* 0xbbc2 */
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#define SDXC_IntDoneBit (SDXC_AutoCMDDone | SDXC_DataOver | \
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SDXC_CmdDone | SDXC_VolChgDone)
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/* status */
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#define SDXC_RXWLFlag BIT(0)
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#define SDXC_TXWLFlag BIT(1)
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#define SDXC_FIFOEmpty BIT(2)
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#define SDXC_FIFOFull BIT(3)
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#define SDXC_CardPresent BIT(8)
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#define SDXC_CardDataBusy BIT(9)
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#define SDXC_DataFSMBusy BIT(10)
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#define SDXC_DMAReq BIT(31)
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#define SDXC_FIFO_SIZE (16)
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/* Function select */
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#define SDXC_CEATAOn (0xceaaU << 16)
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#define SDXC_SendIrqRsp BIT(0)
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#define SDXC_SDIORdWait BIT(1)
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#define SDXC_AbtRdData BIT(2)
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#define SDXC_SendCCSD BIT(8)
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#define SDXC_SendAutoStopCCSD BIT(9)
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#define SDXC_CEATADevIntEnb BIT(10)
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/* IDMA controller bus mod bit field */
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#define SDXC_IDMACSoftRST BIT(0)
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#define SDXC_IDMACFixBurst BIT(1)
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#define SDXC_IDMACIDMAOn BIT(7)
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#define SDXC_IDMACRefetchDES BIT(31)
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/* IDMA status bit field */
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#define SDXC_IDMACTransmitInt BIT(0)
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#define SDXC_IDMACReceiveInt BIT(1)
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#define SDXC_IDMACFatalBusErr BIT(2)
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#define SDXC_IDMACDesInvalid BIT(4)
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#define SDXC_IDMACCardErrSum BIT(5)
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#define SDXC_IDMACNormalIntSum BIT(8)
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#define SDXC_IDMACAbnormalIntSum BIT(9)
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#define SDXC_IDMACHostAbtInTx BIT(10)
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#define SDXC_IDMACHostAbtInRx BIT(10)
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#define SDXC_IDMACIdle (0U << 13)
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#define SDXC_IDMACSuspend (1U << 13)
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#define SDXC_IDMACDESCRd (2U << 13)
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#define SDXC_IDMACDESCCheck (3U << 13)
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#define SDXC_IDMACRdReqWait (4U << 13)
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#define SDXC_IDMACWrReqWait (5U << 13)
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#define SDXC_IDMACRd (6U << 13)
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#define SDXC_IDMACWr (7U << 13)
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#define SDXC_IDMACDESCClose (8U << 13)
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struct sunxi_idma_des {
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u32 config;
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#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
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#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
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#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
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#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
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#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
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#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
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#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
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/*
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* If the idma-des-size-bits of property is ie 13, bufsize bits are:
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* Bits 0-12: buf1 size
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* Bits 13-25: buf2 size
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* Bits 26-31: not used
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* Since we only ever set buf1 size, we can simply store it directly.
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*/
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u32 buf_size;
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u32 buf_addr_ptr1;
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u32 buf_addr_ptr2;
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};
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struct sunxi_mmc_host {
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struct mmc_host *mmc;
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struct regulator *vmmc;
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/* IO mapping base */
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void __iomem *reg_base;
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spinlock_t lock;
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struct tasklet_struct tasklet;
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/* clock management */
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struct clk *clk_ahb;
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struct clk *clk_mod;
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/* indicator pins */
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int wp_pin;
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int cd_pin;
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int cd_mode;
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#define CARD_DETECT_BY_GPIO_POLL (1) /* mmc detected by gpio check */
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#define CARD_ALWAYS_PRESENT (2) /* mmc always present */
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/* ios information */
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u32 clk_mod_rate;
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u32 bus_width;
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u32 idma_des_size_bits;
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u32 ddr;
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u32 voltage_switching;
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/* irq */
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int irq;
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u32 int_sum;
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u32 sdio_imask;
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/* flags */
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u32 power_on:1;
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u32 io_flag:1;
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u32 wait_dma:1;
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dma_addr_t sg_dma;
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void *sg_cpu;
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struct mmc_request *mrq;
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u32 ferror;
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};
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#define MMC_CLK_400K 0
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#define MMC_CLK_25M 1
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#define MMC_CLK_50M 2
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#define MMC_CLK_50MDDR 3
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#define MMC_CLK_50MDDR_8BIT 4
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#define MMC_CLK_100M 5
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#define MMC_CLK_200M 6
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#define MMC_CLK_MOD_NUM 7
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struct sunxi_mmc_clk_dly {
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u32 mode;
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u32 oclk_dly;
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u32 sclk_dly;
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};
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#endif
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