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openwrtv3/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch

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ipq806x: fix freeze in PCIe code when booting with an old u-boot Old bootloader (same ones which have DT disabled) don't perform any PCIe initialization. The consequence is a freeze during PCIe bring-up on these old u-boot. Same kernel with a newer bootloaders works fine as they contain the corresponding PCIe init code. In this change, we'll add the missing init and make sure the kernel doesn't rely on some preexisting init to get PCIe to work. That includes the following changes: *GPIOs: set function & drive strength *Clocks: add init code for aux & ref clocks *PCIe driver: additional init of the hardware controller Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46557
2015-08-04 23:10:03 +00:00
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
ipq806x: add hwspinlock support This change cherry-picks the following 3 changes from linux-next: *fb7737 hwspinlock/core: add device tree support *19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block *bd5717 hwspinlock: qcom: Correct msb in regmap_field We're also adding a patch to add the hardware spinlock device nodes on IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch). Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46655
2015-08-17 06:17:47 +00:00
@@ -341,15 +341,21 @@
ipq806x: fix freeze in PCIe code when booting with an old u-boot Old bootloader (same ones which have DT disabled) don't perform any PCIe initialization. The consequence is a freeze during PCIe bring-up on these old u-boot. Same kernel with a newer bootloaders works fine as they contain the corresponding PCIe init code. In this change, we'll add the missing init and make sure the kernel doesn't rely on some preexisting init to get PCIe to work. That includes the following changes: *GPIOs: set function & drive strength *Clocks: add init code for aux & ref clocks *PCIe driver: additional init of the hardware controller Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46557
2015-08-04 23:10:03 +00:00
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
status = "disabled";
};
ipq806x: add hwspinlock support This change cherry-picks the following 3 changes from linux-next: *fb7737 hwspinlock/core: add device tree support *19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block *bd5717 hwspinlock: qcom: Correct msb in regmap_field We're also adding a patch to add the hardware spinlock device nodes on IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch). Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46655
2015-08-17 06:17:47 +00:00
@@ -382,15 +388,21 @@
ipq806x: fix freeze in PCIe code when booting with an old u-boot Old bootloader (same ones which have DT disabled) don't perform any PCIe initialization. The consequence is a freeze during PCIe bring-up on these old u-boot. Same kernel with a newer bootloaders works fine as they contain the corresponding PCIe init code. In this change, we'll add the missing init and make sure the kernel doesn't rely on some preexisting init to get PCIe to work. That includes the following changes: *GPIOs: set function & drive strength *Clocks: add init code for aux & ref clocks *PCIe driver: additional init of the hardware controller Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46557
2015-08-04 23:10:03 +00:00
clocks = <&gcc PCIE_1_A_CLK>,
<&gcc PCIE_1_H_CLK>,
- <&gcc PCIE_1_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_1_PHY_CLK>,
+ <&gcc PCIE_1_AUX_CLK>,
+ <&gcc PCIE_1_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_1_ACLK_RESET>,
<&gcc PCIE_1_HCLK_RESET>,
<&gcc PCIE_1_POR_RESET>,
<&gcc PCIE_1_PCI_RESET>,
- <&gcc PCIE_1_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_1_PHY_RESET>,
+ <&gcc PCIE_1_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
status = "disabled";
};
ipq806x: add hwspinlock support This change cherry-picks the following 3 changes from linux-next: *fb7737 hwspinlock/core: add device tree support *19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block *bd5717 hwspinlock: qcom: Correct msb in regmap_field We're also adding a patch to add the hardware spinlock device nodes on IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch). Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46655
2015-08-17 06:17:47 +00:00
@@ -423,15 +435,21 @@
ipq806x: fix freeze in PCIe code when booting with an old u-boot Old bootloader (same ones which have DT disabled) don't perform any PCIe initialization. The consequence is a freeze during PCIe bring-up on these old u-boot. Same kernel with a newer bootloaders works fine as they contain the corresponding PCIe init code. In this change, we'll add the missing init and make sure the kernel doesn't rely on some preexisting init to get PCIe to work. That includes the following changes: *GPIOs: set function & drive strength *Clocks: add init code for aux & ref clocks *PCIe driver: additional init of the hardware controller Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46557
2015-08-04 23:10:03 +00:00
clocks = <&gcc PCIE_2_A_CLK>,
<&gcc PCIE_2_H_CLK>,
- <&gcc PCIE_2_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_2_PHY_CLK>,
+ <&gcc PCIE_2_AUX_CLK>,
+ <&gcc PCIE_2_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_2_ACLK_RESET>,
<&gcc PCIE_2_HCLK_RESET>,
<&gcc PCIE_2_POR_RESET>,
<&gcc PCIE_2_PCI_RESET>,
- <&gcc PCIE_2_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_2_PHY_RESET>,
+ <&gcc PCIE_2_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
status = "disabled";
};
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