128 lines
4.9 KiB
Diff
128 lines
4.9 KiB
Diff
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From 184580ac95b7fa05eaf5ee16393ddd6103493d0a Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Wed, 28 Sep 2016 19:01:48 -0700
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Subject: [PATCH] drm/vc4: Add support for double-clocked modes.
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Now that we have infoframes to report the pixel repeat flag, we can
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start using it. Fixes locking the 720x480i and 720x576i modes on my
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Dell 2408WFP. Like the 1920x1080i case, they don't fit properly on
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the screen, though.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 17 +++++++++++------
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drivers/gpu/drm/vc4/vc4_hdmi.c | 16 +++++++++++-----
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drivers/gpu/drm/vc4/vc4_regs.h | 2 ++
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3 files changed, 24 insertions(+), 11 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -371,6 +371,7 @@ static void vc4_crtc_mode_set_nofb(struc
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bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
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vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
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u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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+ u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
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bool debug_dump_regs = false;
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if (debug_dump_regs) {
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@@ -384,14 +385,17 @@ static void vc4_crtc_mode_set_nofb(struc
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CRTC_WRITE(PV_CONTROL, 0);
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CRTC_WRITE(PV_HORZA,
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- VC4_SET_FIELD(mode->htotal - mode->hsync_end,
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+ VC4_SET_FIELD((mode->htotal -
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+ mode->hsync_end) * pixel_rep,
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PV_HORZA_HBP) |
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- VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
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+ VC4_SET_FIELD((mode->hsync_end -
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+ mode->hsync_start) * pixel_rep,
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PV_HORZA_HSYNC));
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CRTC_WRITE(PV_HORZB,
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- VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
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+ VC4_SET_FIELD((mode->hsync_start -
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+ mode->hdisplay) * pixel_rep,
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PV_HORZB_HFP) |
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- VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
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+ VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
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CRTC_WRITE(PV_VERTA,
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VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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@@ -426,7 +430,7 @@ static void vc4_crtc_mode_set_nofb(struc
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PV_VCONTROL_CONTINUOUS |
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(is_dsi ? PV_VCONTROL_DSI : 0) |
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PV_VCONTROL_INTERLACE |
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- VC4_SET_FIELD(mode->htotal / 2,
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+ VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
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PV_VCONTROL_ODD_DELAY));
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CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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} else {
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@@ -435,12 +439,13 @@ static void vc4_crtc_mode_set_nofb(struc
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(is_dsi ? PV_VCONTROL_DSI : 0));
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}
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- CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
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+ CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
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CRTC_WRITE(PV_CONTROL,
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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VC4_SET_FIELD(vc4_get_fifo_full_level(format),
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PV_CONTROL_FIFO_LEVEL) |
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+ VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
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PV_CONTROL_CLR_AT_START |
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PV_CONTROL_TRIGGER_UNDERFLOW |
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PV_CONTROL_WAIT_HSTART |
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -411,6 +411,7 @@ static void vc4_hdmi_encoder_mode_set(st
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bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
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bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
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bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
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+ u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
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u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
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VC4_HDMI_VERTA_VSP) |
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VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
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@@ -433,7 +434,8 @@ static void vc4_hdmi_encoder_mode_set(st
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HD_WRITE(VC4_HD_VID_CTL, 0);
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- clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
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+ clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000 *
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+ ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
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HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
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HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
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@@ -443,14 +445,18 @@ static void vc4_hdmi_encoder_mode_set(st
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HDMI_WRITE(VC4_HDMI_HORZA,
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(vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
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(hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
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- VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
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+ VC4_SET_FIELD(mode->hdisplay * pixel_rep,
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+ VC4_HDMI_HORZA_HAP));
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HDMI_WRITE(VC4_HDMI_HORZB,
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- VC4_SET_FIELD(mode->htotal - mode->hsync_end,
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+ VC4_SET_FIELD((mode->htotal -
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+ mode->hsync_end) * pixel_rep,
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VC4_HDMI_HORZB_HBP) |
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- VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
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+ VC4_SET_FIELD((mode->hsync_end -
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+ mode->hsync_start) * pixel_rep,
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VC4_HDMI_HORZB_HSP) |
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- VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
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+ VC4_SET_FIELD((mode->hsync_start -
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+ mode->hdisplay) * pixel_rep,
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VC4_HDMI_HORZB_HFP));
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HDMI_WRITE(VC4_HDMI_VERTA0, verta);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -175,6 +175,8 @@
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# define PV_CONTROL_CLR_AT_START BIT(14)
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# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
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# define PV_CONTROL_WAIT_HSTART BIT(12)
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+# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
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+# define PV_CONTROL_PIXEL_REP_SHIFT 4
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# define PV_CONTROL_CLK_SELECT_DSI_VEC 0
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# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
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# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
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