30 lines
1 KiB
Diff
30 lines
1 KiB
Diff
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From 0f15814bcdf59f10b708a3fba636acb089e9a4f1 Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Thu, 30 Mar 2017 15:34:39 +0200
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Subject: [PATCH] MIPS: ath79: fix AR724X_PLL_REG_PCIE_CONFIG offset
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According to the QCA u-boot source the "PCIE Phase Lock Loop
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Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
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QCA955X and QCA956X at offset 0x10.
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Since the PCIE PLL config register is only defined for the AR724x fix
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only this value. The value is wrong since the day it was added and isn't
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yet used by any driver.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -167,7 +167,7 @@
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#define AR71XX_AHB_DIV_MASK 0x7
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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-#define AR724X_PLL_REG_PCIE_CONFIG 0x18
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+#define AR724X_PLL_REG_PCIE_CONFIG 0x10
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#define AR724X_PLL_FB_SHIFT 0
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#define AR724X_PLL_FB_MASK 0x3ff
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