76 lines
2.3 KiB
Diff
76 lines
2.3 KiB
Diff
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From 6632619d49f0f90c4d74caad67749864f154cae4 Mon Sep 17 00:00:00 2001
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From: Georgi Djakov <gdjakov@mm-sol.com>
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Date: Fri, 31 Jan 2014 16:21:56 +0200
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Subject: [PATCH 090/182] ARM: dts: msm: Add SDHC controller nodes for MSM8974
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and DB8074 board
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Add support for the 2 SDHC controllers on the DB8074 board. The first
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controller (at 0xf9824900) is connected to an on board soldered eMMC.
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The second controller (at 0xf98a4900) is connected to a uSD card slot.
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Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 13 +++++++++++++
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arch/arm/boot/dts/qcom-msm8974.dtsi | 22 ++++++++++++++++++++++
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2 files changed, 35 insertions(+)
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diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
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index 13ac3e2..92320c4 100644
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--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
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+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
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@@ -3,4 +3,17 @@
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/ {
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model = "Qualcomm APQ8074 Dragonboard";
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compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
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+
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+ soc: soc {
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+ sdhci@f9824900 {
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+ bus-width = <8>;
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+ non-removable;
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+ status = "ok";
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+ };
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+
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+ sdhci@f98a4900 {
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+ cd-gpios = <&msmgpio 62 0x1>;
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+ bus-width = <4>;
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+ };
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+ };
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};
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diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
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index 23aa387..c530a33 100644
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--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
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@@ -192,6 +192,28 @@
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clock-names = "core", "iface";
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};
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+ sdhci@f9824900 {
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+ compatible = "qcom,sdhci-msm-v4";
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+ reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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+ reg-names = "hc_mem", "core_mem";
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+ interrupts = <0 123 0>, <0 138 0>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ sdhci@f98a4900 {
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+ compatible = "qcom,sdhci-msm-v4";
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+ reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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+ reg-names = "hc_mem", "core_mem";
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+ interrupts = <0 125 0>, <0 221 0>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+ clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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rng@f9bff000 {
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compatible = "qcom,prng";
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reg = <0xf9bff000 0x200>;
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--
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1.7.10.4
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