2015-04-01 08:32:03 +00:00
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: spi: qup: Add DMA capabilities
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From: Andy Gross <agross@codeaurora.org>
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X-Patchwork-Id: 4432401
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Message-Id: <1403816781-31008-1-git-send-email-agross@codeaurora.org>
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To: Mark Brown <broonie@kernel.org>
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Cc: linux-spi@vger.kernel.org, Sagar Dharia <sdharia@codeaurora.org>,
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Daniel Sneddon <dsneddon@codeaurora.org>,
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Bjorn Andersson <bjorn.andersson@sonymobile.com>,
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"Ivan T. Ivanov" <iivanov@mm-sol.com>,
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linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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linux-arm-msm@vger.kernel.org, Andy Gross <agross@codeaurora.org>
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Date: Thu, 26 Jun 2014 16:06:21 -0500
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This patch adds DMA capabilities to the spi-qup driver. If DMA channels are
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present, the QUP will use DMA instead of block mode for transfers to/from SPI
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peripherals for transactions larger than the length of a block.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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.../devicetree/bindings/spi/qcom,spi-qup.txt | 10 +
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drivers/spi/spi-qup.c | 361 ++++++++++++++++++--
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2 files changed, 350 insertions(+), 21 deletions(-)
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--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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@@ -27,6 +27,11 @@ Optional properties:
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- spi-max-frequency: Specifies maximum SPI clock frequency,
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Units - Hz. Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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+- dmas : Two DMA channel specifiers following the convention outlined
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+ in bindings/dma/dma.txt
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+- dma-names: Names for the dma channels, if present. There must be at
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+ least one channel named "tx" for transmit and named "rx" for
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+ receive.
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- num-cs: total number of chipselects
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- cs-gpios: should specify GPIOs used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child
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@@ -51,6 +56,10 @@ Example:
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clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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+ dmas = <&blsp2_bam 2>,
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+ <&blsp2_bam 3>;
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+ dma-names = "rx", "tx";
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+
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pinctrl-names = "default";
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pinctrl-0 = <&spi8_default>;
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -22,6 +22,8 @@
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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+#include <linux/dmaengine.h>
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+#include <linux/dma-mapping.h>
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#define QUP_CONFIG 0x0000
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#define QUP_STATE 0x0004
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@@ -116,6 +118,8 @@
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#define SPI_NUM_CHIPSELECTS 4
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+#define SPI_MAX_XFER (SZ_64K - 64)
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+
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/* high speed mode is when bus rate is greater then 26MHz */
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#define SPI_HS_MIN_RATE 26000000
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#define SPI_MAX_RATE 50000000
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@@ -143,6 +147,17 @@ struct spi_qup {
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int tx_bytes;
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int rx_bytes;
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int qup_v1;
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+
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+ int use_dma;
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+
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+ struct dma_chan *rx_chan;
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+ struct dma_slave_config rx_conf;
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+ struct dma_chan *tx_chan;
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+ struct dma_slave_config tx_conf;
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+ dma_addr_t rx_dma;
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+ dma_addr_t tx_dma;
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+ void *dummy;
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+ atomic_t dma_outstanding;
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};
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@@ -266,6 +281,221 @@ static void spi_qup_fifo_write(struct sp
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}
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}
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+static void qup_dma_callback(void *data)
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+{
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+ struct spi_qup *controller = data;
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+
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+ if (atomic_dec_and_test(&controller->dma_outstanding))
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+ complete(&controller->done);
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+}
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+
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+static int spi_qup_do_dma(struct spi_qup *controller, struct spi_transfer *xfer)
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+{
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+ struct dma_async_tx_descriptor *rxd, *txd;
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+ dma_cookie_t rx_cookie, tx_cookie;
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+ u32 xfer_len, rx_align = 0, tx_align = 0, n_words;
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+ struct scatterlist tx_sg[2], rx_sg[2];
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+ int ret = 0;
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+ u32 bytes_to_xfer = xfer->len;
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+ u32 offset = 0;
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+ u32 rx_nents = 0, tx_nents = 0;
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+ dma_addr_t rx_dma = 0, tx_dma = 0, rx_dummy_dma = 0, tx_dummy_dma = 0;
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+
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+
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+ if (xfer->rx_buf) {
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+ rx_dma = dma_map_single(controller->dev, xfer->rx_buf,
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+ xfer->len, DMA_FROM_DEVICE);
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+
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+ if (dma_mapping_error(controller->dev, rx_dma)) {
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+ ret = -ENOMEM;
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+ return ret;
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+ }
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+
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+ /* check to see if we need dummy buffer for leftover bytes */
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+ rx_align = xfer->len % controller->in_blk_sz;
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+ if (rx_align) {
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+ rx_dummy_dma = dma_map_single(controller->dev,
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+ controller->dummy, controller->in_fifo_sz,
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+ DMA_FROM_DEVICE);
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+
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+ if (dma_mapping_error(controller->dev, rx_dummy_dma)) {
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+ ret = -ENOMEM;
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+ goto err_map_rx_dummy;
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+ }
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+ }
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+ }
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+
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+ if (xfer->tx_buf) {
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+ tx_dma = dma_map_single(controller->dev,
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+ (void *)xfer->tx_buf, xfer->len, DMA_TO_DEVICE);
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+
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+ if (dma_mapping_error(controller->dev, tx_dma)) {
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+ ret = -ENOMEM;
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+ goto err_map_tx;
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+ }
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+
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+ /* check to see if we need dummy buffer for leftover bytes */
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+ tx_align = xfer->len % controller->out_blk_sz;
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+ if (tx_align) {
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+ memcpy(controller->dummy + SZ_1K,
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+ xfer->tx_buf + xfer->len - tx_align,
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+ tx_align);
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+ memset(controller->dummy + SZ_1K + tx_align, 0,
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+ controller->out_blk_sz - tx_align);
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+
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+ tx_dummy_dma = dma_map_single(controller->dev,
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+ controller->dummy + SZ_1K,
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+ controller->out_blk_sz, DMA_TO_DEVICE);
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+
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+ if (dma_mapping_error(controller->dev, tx_dummy_dma)) {
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+ ret = -ENOMEM;
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+ goto err_map_tx_dummy;
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+ }
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+ }
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+ }
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+
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+ atomic_set(&controller->dma_outstanding, 0);
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+
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+ while (bytes_to_xfer > 0) {
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+ xfer_len = min_t(u32, bytes_to_xfer, SPI_MAX_XFER);
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+ n_words = DIV_ROUND_UP(xfer_len, controller->w_size);
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+
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+ /* write out current word count to controller */
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+ writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
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+
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+ reinit_completion(&controller->done);
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+
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+ if (xfer->tx_buf) {
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+ /* recalc align for each transaction */
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+ tx_align = xfer_len % controller->out_blk_sz;
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+
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+ if (tx_align)
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+ tx_nents = 2;
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+ else
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+ tx_nents = 1;
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+
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+ /* initialize scatterlists */
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+ sg_init_table(tx_sg, tx_nents);
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+ sg_dma_len(&tx_sg[0]) = xfer_len - tx_align;
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+ sg_dma_address(&tx_sg[0]) = tx_dma + offset;
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+
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+ /* account for non block size transfer */
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+ if (tx_align) {
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+ sg_dma_len(&tx_sg[1]) = controller->out_blk_sz;
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+ sg_dma_address(&tx_sg[1]) = tx_dummy_dma;
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+ }
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+
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+ txd = dmaengine_prep_slave_sg(controller->tx_chan,
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+ tx_sg, tx_nents, DMA_MEM_TO_DEV, 0);
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+ if (!txd) {
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+ ret = -ENOMEM;
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+ goto err_unmap;
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+ }
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+
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+ atomic_inc(&controller->dma_outstanding);
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+
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+ txd->callback = qup_dma_callback;
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+ txd->callback_param = controller;
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+
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+ tx_cookie = dmaengine_submit(txd);
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+
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+ dma_async_issue_pending(controller->tx_chan);
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+ }
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+
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+ if (xfer->rx_buf) {
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+ /* recalc align for each transaction */
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+ rx_align = xfer_len % controller->in_blk_sz;
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+
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+ if (rx_align)
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+ rx_nents = 2;
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+ else
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+ rx_nents = 1;
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+
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+ /* initialize scatterlists */
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+ sg_init_table(rx_sg, rx_nents);
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+ sg_dma_address(&rx_sg[0]) = rx_dma + offset;
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+ sg_dma_len(&rx_sg[0]) = xfer_len - rx_align;
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+
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+ /* account for non block size transfer */
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+ if (rx_align) {
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+ sg_dma_len(&rx_sg[1]) = controller->in_blk_sz;
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+ sg_dma_address(&rx_sg[1]) = rx_dummy_dma;
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+ }
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+
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+ rxd = dmaengine_prep_slave_sg(controller->rx_chan,
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+ rx_sg, rx_nents, DMA_DEV_TO_MEM, 0);
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+ if (!rxd) {
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+ ret = -ENOMEM;
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+ goto err_unmap;
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+ }
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+
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+ atomic_inc(&controller->dma_outstanding);
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+
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+ rxd->callback = qup_dma_callback;
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+ rxd->callback_param = controller;
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+
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+ rx_cookie = dmaengine_submit(rxd);
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+
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+ dma_async_issue_pending(controller->rx_chan);
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+ }
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+
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+ if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
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+ dev_warn(controller->dev, "cannot set EXECUTE state\n");
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+ goto err_unmap;
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+ }
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+
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+ if (!wait_for_completion_timeout(&controller->done,
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+ msecs_to_jiffies(1000))) {
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+ ret = -ETIMEDOUT;
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+
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+ /* clear out all the DMA transactions */
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+ if (xfer->tx_buf)
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+ dmaengine_terminate_all(controller->tx_chan);
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+ if (xfer->rx_buf)
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+ dmaengine_terminate_all(controller->rx_chan);
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+
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+ goto err_unmap;
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+ }
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+
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+ if (rx_align)
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+ memcpy(xfer->rx_buf + offset + xfer->len - rx_align,
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+ controller->dummy, rx_align);
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+
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+ /* adjust remaining bytes to transfer */
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+ bytes_to_xfer -= xfer_len;
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+ offset += xfer_len;
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+
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+
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+ /* reset mini-core state so we can program next transaction */
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+ if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
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+ dev_err(controller->dev, "cannot set RESET state\n");
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+ goto err_unmap;
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+ }
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+ }
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+
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+ ret = 0;
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+
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+err_unmap:
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+ if (tx_align)
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+ dma_unmap_single(controller->dev, tx_dummy_dma,
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+ controller->out_fifo_sz, DMA_TO_DEVICE);
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+err_map_tx_dummy:
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+ if (xfer->tx_buf)
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+ dma_unmap_single(controller->dev, tx_dma, xfer->len,
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+ DMA_TO_DEVICE);
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+err_map_tx:
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+ if (rx_align)
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+ dma_unmap_single(controller->dev, rx_dummy_dma,
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+ controller->in_fifo_sz, DMA_FROM_DEVICE);
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+err_map_rx_dummy:
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+ if (xfer->rx_buf)
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+ dma_unmap_single(controller->dev, rx_dma, xfer->len,
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+ DMA_FROM_DEVICE);
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+
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+ return ret;
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+}
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+
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static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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{
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struct spi_qup *controller = dev_id;
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@@ -315,11 +545,13 @@ static irqreturn_t spi_qup_qup_irq(int i
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error = -EIO;
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}
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- if (opflags & QUP_OP_IN_SERVICE_FLAG)
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- spi_qup_fifo_read(controller, xfer);
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+ if (!controller->use_dma) {
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+ if (opflags & QUP_OP_IN_SERVICE_FLAG)
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+ spi_qup_fifo_read(controller, xfer);
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- if (opflags & QUP_OP_OUT_SERVICE_FLAG)
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- spi_qup_fifo_write(controller, xfer);
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+ if (opflags & QUP_OP_OUT_SERVICE_FLAG)
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+ spi_qup_fifo_write(controller, xfer);
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+ }
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spin_lock_irqsave(&controller->lock, flags);
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controller->error = error;
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@@ -339,6 +571,8 @@ static int spi_qup_io_config(struct spi_
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struct spi_qup *controller = spi_master_get_devdata(spi->master);
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2015-05-23 15:27:28 +00:00
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u32 config, iomode, mode, control;
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2015-04-01 08:32:03 +00:00
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|
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int ret, n_words, w_size;
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+ size_t dma_align = dma_get_cache_alignment();
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+ u32 dma_available = 0;
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if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
|
|
|
|
dev_err(controller->dev, "too big size for loopback %d > %d\n",
|
|
|
|
@@ -367,6 +601,11 @@ static int spi_qup_io_config(struct spi_
|
|
|
|
n_words = xfer->len / w_size;
|
|
|
|
controller->w_size = w_size;
|
|
|
|
|
|
|
|
+ if (controller->rx_chan &&
|
|
|
|
+ IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
|
|
|
|
+ IS_ALIGNED((size_t)xfer->rx_buf, dma_align))
|
|
|
|
+ dma_available = 1;
|
|
|
|
+
|
|
|
|
if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
|
|
|
|
mode = QUP_IO_M_MODE_FIFO;
|
|
|
|
writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
|
|
|
|
@@ -374,19 +613,31 @@ static int spi_qup_io_config(struct spi_
|
|
|
|
/* must be zero for FIFO */
|
|
|
|
writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
|
|
|
|
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
|
|
|
|
- } else {
|
|
|
|
+ controller->use_dma = 0;
|
|
|
|
+ } else if (!dma_available) {
|
|
|
|
mode = QUP_IO_M_MODE_BLOCK;
|
|
|
|
writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
|
|
|
|
writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
|
|
|
|
/* must be zero for BLOCK and BAM */
|
|
|
|
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
|
|
|
|
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
|
|
|
|
+ controller->use_dma = 0;
|
|
|
|
+ } else {
|
|
|
|
+ mode = QUP_IO_M_MODE_DMOV;
|
|
|
|
+ writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
|
|
|
|
+ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
|
|
|
|
+ controller->use_dma = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
|
|
|
|
/* Set input and output transfer mode */
|
|
|
|
iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
|
|
|
|
- iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
|
|
|
|
+
|
|
|
|
+ if (!controller->use_dma)
|
|
|
|
+ iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
|
|
|
|
+ else
|
|
|
|
+ iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
|
|
|
|
+
|
|
|
|
iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
|
|
|
|
iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
|
|
|
|
|
2015-05-23 15:27:28 +00:00
|
|
|
@@ -428,6 +679,14 @@ static int spi_qup_io_config(struct spi_
|
2015-04-01 08:32:03 +00:00
|
|
|
config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
|
|
|
|
config |= xfer->bits_per_word - 1;
|
|
|
|
config |= QUP_CONFIG_SPI_MODE;
|
|
|
|
+
|
|
|
|
+ if (controller->use_dma) {
|
|
|
|
+ if (!xfer->tx_buf)
|
|
|
|
+ config |= QUP_CONFIG_NO_OUTPUT;
|
|
|
|
+ if (!xfer->rx_buf)
|
|
|
|
+ config |= QUP_CONFIG_NO_INPUT;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
writel_relaxed(config, controller->base + QUP_CONFIG);
|
|
|
|
|
|
|
|
/* only write to OPERATIONAL_MASK when register is present */
|
2015-05-23 15:27:28 +00:00
|
|
|
@@ -461,25 +720,29 @@ static int spi_qup_transfer_one(struct s
|
2015-04-01 08:32:03 +00:00
|
|
|
controller->tx_bytes = 0;
|
|
|
|
spin_unlock_irqrestore(&controller->lock, flags);
|
|
|
|
|
|
|
|
- if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
|
|
|
|
- dev_warn(controller->dev, "cannot set RUN state\n");
|
|
|
|
- goto exit;
|
|
|
|
- }
|
|
|
|
+ if (controller->use_dma) {
|
|
|
|
+ ret = spi_qup_do_dma(controller, xfer);
|
|
|
|
+ } else {
|
|
|
|
+ if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
|
|
|
|
+ dev_warn(controller->dev, "cannot set RUN state\n");
|
|
|
|
+ goto exit;
|
|
|
|
+ }
|
|
|
|
|
|
|
|
- if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
|
|
|
|
- dev_warn(controller->dev, "cannot set PAUSE state\n");
|
|
|
|
- goto exit;
|
|
|
|
- }
|
|
|
|
+ if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
|
|
|
|
+ dev_warn(controller->dev, "cannot set PAUSE state\n");
|
|
|
|
+ goto exit;
|
|
|
|
+ }
|
|
|
|
|
|
|
|
- spi_qup_fifo_write(controller, xfer);
|
|
|
|
+ spi_qup_fifo_write(controller, xfer);
|
|
|
|
|
|
|
|
- if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
|
|
|
|
- dev_warn(controller->dev, "cannot set EXECUTE state\n");
|
|
|
|
- goto exit;
|
|
|
|
- }
|
|
|
|
+ if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
|
|
|
|
+ dev_warn(controller->dev, "cannot set EXECUTE state\n");
|
|
|
|
+ goto exit;
|
|
|
|
+ }
|
|
|
|
|
|
|
|
- if (!wait_for_completion_timeout(&controller->done, timeout))
|
|
|
|
- ret = -ETIMEDOUT;
|
|
|
|
+ if (!wait_for_completion_timeout(&controller->done, timeout))
|
|
|
|
+ ret = -ETIMEDOUT;
|
|
|
|
+ }
|
|
|
|
exit:
|
|
|
|
spi_qup_set_state(controller, QUP_STATE_RESET);
|
|
|
|
spin_lock_irqsave(&controller->lock, flags);
|
2015-05-23 15:27:28 +00:00
|
|
|
@@ -563,6 +826,7 @@ static int spi_qup_probe(struct platform
|
2015-04-01 08:32:03 +00:00
|
|
|
master->transfer_one = spi_qup_transfer_one;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
|
|
master->auto_runtime_pm = true;
|
|
|
|
+ master->dma_alignment = dma_get_cache_alignment();
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
|
2015-05-23 15:27:28 +00:00
|
|
|
@@ -628,6 +892,56 @@ static int spi_qup_probe(struct platform
|
2015-04-01 08:32:03 +00:00
|
|
|
QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
|
|
|
|
base + QUP_ERROR_FLAGS_EN);
|
|
|
|
|
|
|
|
+ /* allocate dma resources, if available */
|
|
|
|
+ controller->rx_chan = dma_request_slave_channel(&pdev->dev, "rx");
|
|
|
|
+ if (controller->rx_chan) {
|
|
|
|
+ controller->tx_chan =
|
|
|
|
+ dma_request_slave_channel(&pdev->dev, "tx");
|
|
|
|
+
|
|
|
|
+ if (!controller->tx_chan) {
|
|
|
|
+ dev_err(&pdev->dev, "Failed to allocate dma tx chan");
|
|
|
|
+ dma_release_channel(controller->rx_chan);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* set DMA parameters */
|
|
|
|
+ controller->rx_conf.device_fc = 1;
|
|
|
|
+ controller->rx_conf.src_addr = res->start + QUP_INPUT_FIFO;
|
|
|
|
+ controller->rx_conf.src_maxburst = controller->in_blk_sz;
|
|
|
|
+
|
|
|
|
+ controller->tx_conf.device_fc = 1;
|
|
|
|
+ controller->tx_conf.dst_addr = res->start + QUP_OUTPUT_FIFO;
|
|
|
|
+ controller->tx_conf.dst_maxburst = controller->out_blk_sz;
|
|
|
|
+
|
|
|
|
+ if (dmaengine_slave_config(controller->rx_chan,
|
|
|
|
+ &controller->rx_conf)) {
|
|
|
|
+ dev_err(&pdev->dev, "failed to configure RX channel\n");
|
|
|
|
+
|
|
|
|
+ dma_release_channel(controller->rx_chan);
|
|
|
|
+ dma_release_channel(controller->tx_chan);
|
|
|
|
+ controller->tx_chan = NULL;
|
|
|
|
+ controller->rx_chan = NULL;
|
|
|
|
+ } else if (dmaengine_slave_config(controller->tx_chan,
|
|
|
|
+ &controller->tx_conf)) {
|
|
|
|
+ dev_err(&pdev->dev, "failed to configure TX channel\n");
|
|
|
|
+
|
|
|
|
+ dma_release_channel(controller->rx_chan);
|
|
|
|
+ dma_release_channel(controller->tx_chan);
|
|
|
|
+ controller->tx_chan = NULL;
|
|
|
|
+ controller->rx_chan = NULL;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ controller->dummy = devm_kmalloc(controller->dev, PAGE_SIZE,
|
|
|
|
+ GFP_KERNEL);
|
|
|
|
+
|
|
|
|
+ if (!controller->dummy) {
|
|
|
|
+ dma_release_channel(controller->rx_chan);
|
|
|
|
+ dma_release_channel(controller->tx_chan);
|
|
|
|
+ controller->tx_chan = NULL;
|
|
|
|
+ controller->rx_chan = NULL;
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+
|
|
|
|
writel_relaxed(0, base + SPI_CONFIG);
|
|
|
|
writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
|
|
|
|
|
2015-05-23 15:27:28 +00:00
|
|
|
@@ -740,6 +1054,11 @@ static int spi_qup_remove(struct platfor
|
2015-04-01 08:32:03 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
+ if (controller->rx_chan)
|
|
|
|
+ dma_release_channel(controller->rx_chan);
|
|
|
|
+ if (controller->tx_chan)
|
|
|
|
+ dma_release_channel(controller->tx_chan);
|
|
|
|
+
|
|
|
|
clk_disable_unprepare(controller->cclk);
|
|
|
|
clk_disable_unprepare(controller->iclk);
|
|
|
|
|