2016-04-01 07:11:18 +00:00
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From 429b5becfb1e4aacf392c4b246a17b83faad3072 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 29 Mar 2016 14:32:07 +0200
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2016-04-09 10:25:08 +00:00
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Subject: [PATCH 67/81] net: mediatek: update the IRQ part of the binding
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2016-04-01 07:11:18 +00:00
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document
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The current binding document only describes a single interrupt. Update the
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document by adding the 2 other interrupts.
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The driver currently only uses a single interrupt. The HW is however able
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to using IRQ grouping to split TX and RX onto separate GIC irqs.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Rob Herring <robh@kernel.org>
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---
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Documentation/devicetree/bindings/net/mediatek-net.txt | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
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index 5ca7929..2f142be 100644
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--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
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+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
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@@ -9,7 +9,7 @@ have dual GMAC each represented by a child node..
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Required properties:
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- compatible: Should be "mediatek,mt7623-eth"
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- reg: Address and length of the register set for the device
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-- interrupts: Should contain the frame engines interrupt
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+- interrupts: Should contain the three frame engines interrupts
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- clocks: the clock used by the core
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- clock-names: the names of the clock listed in the clocks property. These are
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"ethif", "esw", "gp2", "gp1"
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@@ -42,7 +42,9 @@ eth: ethernet@1b100000 {
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<ðsys CLK_ETHSYS_GP2>,
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<ðsys CLK_ETHSYS_GP1>;
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clock-names = "ethif", "esw", "gp2", "gp1";
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- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
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+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
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+ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
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+ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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resets = <ðsys MT2701_ETHSYS_ETH_RST>;
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reset-names = "eth";
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--
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1.7.10.4
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