40 lines
1.1 KiB
Diff
40 lines
1.1 KiB
Diff
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--- a/arch/powerpc/boot/cuboot-openrb-light.c
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+++ b/arch/powerpc/boot/cuboot-openrb-light.c
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@@ -22,8 +22,36 @@
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static bd_t bd;
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+static void fixup_cf_card(void)
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+{
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+#define DCRN_CPC0_PCI_BASE 0xf9
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+#define CF_CS0_BASE 0xff100000
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+#define CF_CS1_BASE 0xff200000
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+
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+ /* Turn on PerWE instead of PCIsomething */
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+ mtdcr(DCRN_CPC0_PCI_BASE,
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+ mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
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+
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+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
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+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
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+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
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+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
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+
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+#undef DCRN_CPC0_PCI_BASE
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+#undef CF_CS0_BASE
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+#undef CF_CS1_BASE
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+}
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+
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static void openrb_light_fixups(void)
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{
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+ fixup_cf_card();
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ibm405ep_fixup_clocks(33333000);
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
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