145 lines
4.4 KiB
Diff
145 lines
4.4 KiB
Diff
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From 26d82e0081aa6f0c7db5e4bb5b154b7c528cb8d6 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 14 Nov 2013 18:25:39 -0300
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Subject: [PATCH 153/203] mtd: nand: pxa3xx: Add ECC BCH correctable errors
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detection
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This commit extends the ECC correctable error detection to include
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ECC BCH errors. The number of BCH correctable errors can be any up to 16,
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and the actual value is exposed in the NDSR register.
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Therefore, we change some symbol names to refer to correctable or
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uncorrectable (instead of single-bit or double-bit as it was in the
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Hamming case) and while at it, cleanup the detection code slightly.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 57 ++++++++++++++++++++++++++----------------
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1 file changed, 35 insertions(+), 22 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -85,6 +85,9 @@
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#define NDCR_INT_MASK (0xFFF)
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#define NDSR_MASK (0xfff)
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+#define NDSR_ERR_CNT_OFF (16)
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+#define NDSR_ERR_CNT_MASK (0x1f)
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+#define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
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#define NDSR_RDY (0x1 << 12)
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#define NDSR_FLASH_RDY (0x1 << 11)
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#define NDSR_CS0_PAGED (0x1 << 10)
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@@ -93,8 +96,8 @@
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#define NDSR_CS1_CMDD (0x1 << 7)
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#define NDSR_CS0_BBD (0x1 << 6)
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#define NDSR_CS1_BBD (0x1 << 5)
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-#define NDSR_DBERR (0x1 << 4)
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-#define NDSR_SBERR (0x1 << 3)
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+#define NDSR_UNCORERR (0x1 << 4)
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+#define NDSR_CORERR (0x1 << 3)
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#define NDSR_WRDREQ (0x1 << 2)
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#define NDSR_RDDREQ (0x1 << 1)
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#define NDSR_WRCMDREQ (0x1)
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@@ -135,9 +138,9 @@ enum {
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ERR_NONE = 0,
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ERR_DMABUSERR = -1,
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ERR_SENDCMD = -2,
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- ERR_DBERR = -3,
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+ ERR_UNCORERR = -3,
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ERR_BBERR = -4,
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- ERR_SBERR = -5,
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+ ERR_CORERR = -5,
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};
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enum {
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@@ -221,6 +224,8 @@ struct pxa3xx_nand_info {
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unsigned int oob_size;
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unsigned int spare_size;
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unsigned int ecc_size;
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+ unsigned int ecc_err_cnt;
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+ unsigned int max_bitflips;
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int retcode;
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/* cached register value */
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@@ -571,10 +576,25 @@ static irqreturn_t pxa3xx_nand_irq(int i
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status = nand_readl(info, NDSR);
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- if (status & NDSR_DBERR)
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- info->retcode = ERR_DBERR;
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- if (status & NDSR_SBERR)
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- info->retcode = ERR_SBERR;
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+ if (status & NDSR_UNCORERR)
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+ info->retcode = ERR_UNCORERR;
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+ if (status & NDSR_CORERR) {
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+ info->retcode = ERR_CORERR;
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+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
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+ info->ecc_bch)
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+ info->ecc_err_cnt = NDSR_ERR_CNT(status);
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+ else
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+ info->ecc_err_cnt = 1;
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+
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+ /*
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+ * Each chunk composing a page is corrected independently,
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+ * and we need to store maximum number of corrected bitflips
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+ * to return it to the MTD layer in ecc.read_page().
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+ */
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+ info->max_bitflips = max_t(unsigned int,
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+ info->max_bitflips,
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+ info->ecc_err_cnt);
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+ }
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if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
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/* whether use dma to transfer data */
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if (info->use_dma) {
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@@ -672,6 +692,7 @@ static void prepare_start_command(struct
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info->use_ecc = 0;
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info->use_spare = 1;
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info->retcode = ERR_NONE;
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+ info->ecc_err_cnt = 0;
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info->ndcb3 = 0;
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switch (command) {
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@@ -1053,26 +1074,18 @@ static int pxa3xx_nand_read_page_hwecc(s
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{
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struct pxa3xx_nand_host *host = mtd->priv;
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struct pxa3xx_nand_info *info = host->info_data;
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- int max_bitflips = 0;
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chip->read_buf(mtd, buf, mtd->writesize);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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- if (info->retcode == ERR_SBERR) {
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- switch (info->use_ecc) {
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- case 1:
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- max_bitflips = 1;
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- mtd->ecc_stats.corrected++;
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- break;
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- case 0:
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- default:
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- break;
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- }
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- } else if (info->retcode == ERR_DBERR) {
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+ if (info->retcode == ERR_CORERR && info->use_ecc) {
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+ mtd->ecc_stats.corrected += info->ecc_err_cnt;
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+
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+ } else if (info->retcode == ERR_UNCORERR) {
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/*
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* for blank page (all 0xff), HW will calculate its ECC as
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* 0, which is different from the ECC information within
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- * OOB, ignore such double bit errors
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+ * OOB, ignore such uncorrectable errors
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*/
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if (is_buf_blank(buf, mtd->writesize))
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info->retcode = ERR_NONE;
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@@ -1080,7 +1093,7 @@ static int pxa3xx_nand_read_page_hwecc(s
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mtd->ecc_stats.failed++;
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}
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- return max_bitflips;
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+ return info->max_bitflips;
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}
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static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
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