openwrtv3/target/linux/ramips/patches-4.3/0021-arch-mips-ralink-add-mt7688-detection.patch

From 14ef339843c24bf449d0f6d8bc176368c331c2c8 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 7 Dec 2015 17:29:00 +0100
Subject: [PATCH 21/53] arch: mips: ralink: add mt7688 detection

Signed-off-by: John Crispin <blogic@openwrt.org>
---
 arch/mips/include/asm/mach-ralink/mt7620.h      |    1 +
 arch/mips/include/asm/mach-ralink/ralink_regs.h |    1 +
 arch/mips/ralink/mt7620.c                       |   21 ++++++++++++++++-----
 3 files changed, 18 insertions(+), 5 deletions(-)

--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -17,6 +17,7 @@
 
 #define SYSC_REG_CHIP_NAME0		0x00
 #define SYSC_REG_CHIP_NAME1		0x04
+#define SYSC_REG_EFUSE_CFG		0x08
 #define SYSC_REG_CHIP_REV		0x0c
 #define SYSC_REG_SYSTEM_CONFIG0		0x10
 #define SYSC_REG_SYSTEM_CONFIG1		0x14
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -24,6 +24,7 @@ enum ralink_soc_type {
 	MT762X_SOC_MT7620N,
 	MT762X_SOC_MT7621AT,
 	MT762X_SOC_MT7628AN,
+	MT762X_SOC_MT7688,
 };
 extern enum ralink_soc_type ralink_soc;
 
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc;
 #define CLKCFG_FFRAC_MASK	0x001f
 #define CLKCFG_FFRAC_USB_VAL	0x0003
 
+/* EFUSE bits */
+#define EFUSE_MT7688		0x100000
+
 /* does the board have sdram or ddram */
 static int dram_type;
 
@@ -407,7 +410,7 @@ void __init ralink_clk_init(void)
 #define RINT(x)		((x) / 1000000)
 #define RFRAC(x)	(((x) / 1000) % 1000)
 
-	if (mt762x_soc == MT762X_SOC_MT7628AN) {
+	if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
 		if (xtal_rate == MHZ(40))
 			cpu_rate = MHZ(580);
 		else
@@ -451,7 +454,8 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("10000c00.uartlite", periph_rate);
 	ralink_clk_add("10180000.wmac", xtal_rate);
 
-	if (IS_ENABLED(CONFIG_USB)) {
+	if (IS_ENABLED(CONFIG_USB) &&
+		(mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
 		/*
 		 * When the CPU goes into sleep mode, the BUS clock will be too low for
 		 * USB to function properly
@@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_inf
 			soc_info->compatible = "ralink,mt7620n-soc";
 		}
 	} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
-		mt762x_soc = MT762X_SOC_MT7628AN;
-		name = "MT7628AN";
+		u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
+
+		if (efuse & EFUSE_MT7688) {
+			mt762x_soc = MT762X_SOC_MT7688;
+			name = "MT7688";
+		} else {
+			mt762x_soc = MT762X_SOC_MT7628AN;
+			name = "MT7628AN";
+		}
 		soc_info->compatible = "ralink,mt7628an-soc";
 	} else {
 		panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
@@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_inf
 	pr_info("Digital PMU set to %s control\n",
 		(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
 
-	if (mt762x_soc == MT762X_SOC_MT7628AN)
+	if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
 		rt2880_pinmux_data = mt7628an_pinmux_data;
 	else
 		rt2880_pinmux_data = mt7620a_pinmux_data;